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Wafer test method for discrete device

A discrete device and wafer testing technology, applied in the direction of single semiconductor device testing, components and instruments of electrical measuring instruments, etc., can solve problems affecting test efficiency, etc., and achieve the effect of improving test efficiency

Pending Publication Date: 2022-02-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

It can be seen that such a test will affect the test efficiency

Method used

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  • Wafer test method for discrete device
  • Wafer test method for discrete device
  • Wafer test method for discrete device

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Experimental program
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Embodiment Construction

[0029] Such as image 3 Shown is the flowchart of the wafer testing method of the discrete device of the embodiment of the present invention; the wafer testing method of the discrete device of the embodiment of the present invention comprises the following steps:

[0030] Step 1, the chip is formed on the wafer, including a plurality of discrete device modules on the same chip, each of the discrete device modules has more than one test pad 101, and probes are set according to all the test pads 101 on the chip. The probes on the probe card enable the test pads 101 of each discrete device module on the chip to be contacted by the corresponding probes on the same probe card. For the test pad 101 distribution diagram of the chip with more than one test pad 101 please refer to figure 2 shown.

[0031] In the embodiment of the present invention, the discrete device module includes IGBT, MOSFET, diode, resistance or temperature sensor.

[0032] The IGBT includes a super junction ...

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Abstract

The invention discloses a wafer test method for a discrete device. The method comprises the following steps: 1 a chip is formed on a wafer, a plurality of discrete device modules are arranged on the same chip, each discrete device module is provided with more than one test pad, and probes on a probe card are arranged according to all the test pads on the chip; 2 a switch module is arranged on the test channel corresponding to each probe, and the switch module controls the connection or disconnection of the test channel; and 3 during testing, the probes of the probe card are in contact with all the test pads on the chip, and the switch module is controlled to select the discrete device module needing to be tested for testing. The test efficiency of the discrete device can be improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a wafer testing method for discrete devices. Background technique [0002] In the field of semiconductor chip testing, for discrete device wafer testing, a general discrete device such as an IGBT has three electrode terminals, namely a gate, an emitter and a collector. As long as the three terminals are connected, the corresponding project test can be completed. Such as figure 1 Shown is a top view of a test pad for an existing discrete device with 3 test pads, figure 1 Among the three test pads 101, the three test pads 101 are also marked with G and E respectively. For IGBTs, the test pads 101 corresponding to G represent the test pads 101 corresponding to the gate, and the two test pads 101 corresponding to E are emission The electrode corresponds to the test pad, and the collector is the back electrode, so the collector will be located on th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/26G01R1/073
CPCG01R31/26G01R1/073
Inventor 谢晋春辛吉升
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP