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Precoding design method and system for direct jump based on RISC-V

A technology of RISC-V and design method, which is applied in the field of direct jump precoding design method and system, and can solve problems such as long time

Pending Publication Date: 2022-02-11
SUZHOU RICORE IC TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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then it will take a long time

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  • Precoding design method and system for direct jump based on RISC-V
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  • Precoding design method and system for direct jump based on RISC-V

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Embodiment Construction

[0051] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the figures in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention. Moreover, it needs to be further emphasized here that the preferred technical solutions provided by the following specific examples can be used in cooperation or in combination with each other.

[0052] like Figure 4 , 5 Shown is the sequence diagram of the design after introducing predecode in the present invention and the design flow chart after introducing predecode in the present invention. The precoding design method for direct jump based on RISC-V of the present invent...

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Abstract

The invention discloses a pre-coding design method and system for direct jump based on RISC-V. The method comprises the following steps: S1, accessing a high-speed instruction cache; S2, judging whether the cache is hit or not: if yes, entering the step S3, and if not, entering the step S4; S3, carrying out the decoding on the instruction, and obtaining a branch instruction address; S4, accessing a low-speed cache or a low-speed disk; S5, carrying out the pre-coding on the direct jump branch; S6, backfilling the processed instruction. Compared with the method, the method has the advantage that one cycle can be saved.

Description

technical field [0001] The present invention relates to computer instructions, in particular to a RISC-V-based precoding design method and system for direct jump. Background technique [0002] like figure 1 As shown above, instruction 1 is a branch instruction, then decode and decode in the second clock cycle, get the offset carried by the instruction, and calculate the destination address of the branch instruction in the third clock. Instructions are not fetched until the fourth clock cycle. [0003] The address of the conditional branch is calculated from the address of the instruction itself and the address offset (offset) carried by the instruction itself, so the calculation of the instruction address includes: 1) decoding the instruction; 2) calculating with the address and offset of the instruction; 3) Redirects the address of the processor to the target address. This will cause the processor to generate a bubble (bubble) delay of 2 cycles. [0004] like figure 2...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3836
Inventor 张然王飞姜志颖
Owner SUZHOU RICORE IC TECH LTD