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Multiprocessor peripheral multiplexing circuit and multiplexing method thereof

A technology of multiple processors and multiplexing circuits, applied in the direction of electrical digital data processing, instruments, register devices, etc., can solve problems such as multiple processor multiplexing, and achieve the effect of avoiding conflicts

Active Publication Date: 2022-02-11
10TH RES INST OF CETC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Existing solutions are all aimed at the situation where one processor mounts multiple peripherals, and there are few solutions for multiple processors to multiplex the same peripheral

Method used

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  • Multiprocessor peripheral multiplexing circuit and multiplexing method thereof
  • Multiprocessor peripheral multiplexing circuit and multiplexing method thereof

Examples

Experimental program
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Embodiment Construction

[0017] refer to figure 1 . In the exemplary preferred embodiment described below, a multiprocessor peripheral multiplexing circuit includes: a multiprocessor structure composed of programmable logic units PLU connected between n processing units PU1-PUn and peripherals , n processing units PU1~PUn correspond to the PUPLUIF bus reader-writer 1~PUPLUIF bus reader-writer n connected to the PLU, characterized in that: in the processing unit PLU, the PUPLUIF bus reader-writer 1-PUPLUIF bus reader-writer n are connected Corresponding to the shared peripheral lock control register, the shared peripheral lock status register and the peripheral control and status register group, wherein the shared peripheral lock control register and the shared peripheral lock status register are connected to the shared peripheral lock judger, the peripheral control and The state register group is connected to the multiplexing selector, and the multiplexing selector is connected in series with the act...

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Abstract

The invention discloses a multiprocessor peripheral multiplexing circuit and a multiplexing method thereof, and aims to avoid the conflict that multiple processors access the same peripheral at the same time. According to the technical scheme, in a programmable logic unit (PLU), each PUPLUIF bus reader-writer is provided with a shared peripheral locking control register, a shared peripheral locking state register and a peripheral control and state register set, wherein the shared peripheral locking control register and the shared peripheral locking state register are connected with a shared peripheral locking decision device, the peripheral control and state register set is connected with a multiplexing selector, the multiplexing selector is connected with an actuator in series and is connected with the peripheral, and after receiving an access signal of PUx, the PUPLUIF bus reader-writer x writes data into the shared peripheral locking control register x or the peripheral control and state register set x, or after the access signal of the PUx is received, the value of the shared peripheral locking state register x or the value of the peripheral control and state register set x is returned to the PUx.

Description

technical field [0001] The invention relates to a multiprocessor peripheral multiplexing circuit and a peripheral multiplexing method thereof. Background technique [0002] In an integrated system, in order to increase the versatility and flexibility of hardware modules, it is necessary for multiple processors to multiplex the same peripheral hardware. Existing solutions are all aimed at the situation where one processor mounts multiple peripherals, and there are few solutions for multiple processors to multiplex the same peripheral. Contents of the invention [0003] The object of the present invention is to provide a multiprocessor peripheral multiplexing circuit capable of avoiding the conflict of multiprocessors accessing the same peripheral at the same time, aiming at the shortcomings of the prior art. [0004] In order to achieve the above object, a kind of multiprocessor peripheral multiplexing circuit provided by the present invention includes: a multiprocessor st...

Claims

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Application Information

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IPC IPC(8): G06F13/376G06F13/40G06F9/30
CPCG06F13/376G06F13/4022G06F9/30101G06F9/3012G06F9/30076Y02D10/00
Inventor 邵龙马力科
Owner 10TH RES INST OF CETC
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