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Multi-phase clock generation circuit and analog-to-digital converter

A multi-phase clock and analog-to-digital converter technology, applied in the direction of analog-to-digital converter, analog/digital conversion, code conversion, etc., can solve the problems of large internal propagation delay, wrong timing, etc., achieve sufficient settling time and improve tolerance margin volume effect

Active Publication Date: 2022-02-18
苏州迅芯微电子有限公司
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  • Abstract
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Problems solved by technology

[0012] The purpose of the present invention is to provide a multi-phase clock generation circuit, which can compromise the shift register chain internal Unavoidable propagation delay and the condition that the phase interval of each frequency-divided clock signal is small

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Embodiment Construction

[0067] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, those skilled in the art can make some simple modifications and embellishments without creative work, and all other obtained embodiments belong to the protection scope of the present invention.

[0068] Reference in the present invention to an "example" means that a particular feature, structure, or characteristic described in connection with the example can be included in at least one embodiment of the present invention. The presentation of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are independent or alternative embodiments mutually exclusi...

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Abstract

The invention relates to a multi-phase clock generation circuit and an analog-to-digital converter. The multi-phase clock generation circuit comprises a shift register chain. Wherein the shift register chain comprises three or more latches, the latches are divided into at least two groups, the first group comprises one or more latches, and the second group comprises two or more latches; wherein two adjacent latches in each group are cascaded. The multi-phase clock generation circuit can compromise and consider inevitable propagation delay in a shift register chain and the condition that the phase interval of each frequency division clock signal is small.

Description

technical field [0001] The invention relates to a clock generating circuit, in particular to a multi-phase clock generating circuit and an analog-to-digital converter. Background technique [0002] Analog-to-Digital Converters (Analog-to-Digital Converters, ADC) is a circuit that realizes the conversion from analog signals to digital signals, so as to realize the processing of analog signals in nature with digital signal processors, which has a very wide range of application fields and prospects. In order to increase the sampling rate of the ADC, an ADC with a multi-channel time-interleaved architecture has been developed in the industry. In the multi-channel time-interleaved architecture ADC, the multi-phase clock generation circuit used in it plays a vital role in realizing its function and ensuring its performance. [0003] Among them, in order to determine the phase sequence relationship of multiple clock signals, the industry generally adopts a flip-flop-based shift re...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12H03M1/46
CPCH03M1/1245H03M1/121H03M1/462
Inventor 周磊武锦
Owner 苏州迅芯微电子有限公司
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