36results about How to "Reduce latency variance" patented technology

A method is provided for equalizing latency among a group of connections that are being used by the same latency-sensitive application, such as for multi-player network gaming. Delay is added to the packet flow in each connection as necessary at the provider edge router connecting the application server to the network. An NMS connected to the provider edge router continuously monitors the round-trip delay of each connection, determines the additional delay of each connection required to equalize the delays, and informs the provider edge router. The provider edge router buffers traffic on each connection for the respective duration as indicated by the NMS. The NMS may also reroute some of the connections over higher latency resources to reduce the amount of buffering required, which provides the additional advantage of using what might otherwise be less used or economically less valued resources.

According to this data access method to be used in a network system, while the tag information is read out from the tag memory, the data is speculatively read out from the memory unit in the self node device. When the read out tag information shows that the speculatively read out data is not found in any of the cache memories, such speculatively read out data is sent to the processor in the self node device. When the read out tag information shows that the speculatively read out data is found in one of the cache memories, the data existing in such cache memory is acquired and sent to the processor in the self node device and the speculatively readout data is abolished.

A fiber-based ring cavity tunable laser is disclosed in this invention that has full range high speed tuning achieved by combining a optical tunable filter with a period comb-shaped filter with central wavelengths anchored on International Telecommunication Union (ITU) grids. By using segments of dispersion managed fibers with predefined segment lengths the group delay differences are also reduced. The temperature sensitivity of optical transmission is also reduced by arranging the longitudinal axis of different segments of the optical fibers to orient with a relative angular difference, e.g., with an angular difference of ninety degrees.

A delay synchronization loop type clock signal generating circuit includes: a delay line for delaying a first clock signal by a set delay amount and outputting; a delay time length setting unit for setting a delay time length of the delay line, based on phase difference between a second clock signal output from an output terminal and the first clock signal; a phase relation determining unit for determining whether or not the phase relation of the first clock signal and the second clock signal are in a particular phase relation; and a phase inversion/non-inversion unit for performing phase inversion of the first clock signal on a transmission path including the delay line, at the time of detecting the particular phase relation.

A semiconductor device is provided which has a driving circuit operable to drive a circuit that has a delay, the semiconductor device including: an auxiliary driving circuit operable to accelerate drive of the driving circuit, which receives a drive signal of the driving circuit as an input signal.

A display panel having a display region and a non-display region is described. The display panel includes a pixel array, at least one driving device and a plurality of lead lines. The pixel array is disposed in the display region. The driving device is disposed in the non-display region. The lead lines are disposed in the non-display region and are electrically connected to the pixel array and the driving device. The lead lines are arranged into at least one fan-out structure between the pixel array and the driving device. In particular, the (n-1)th lead line has a pitch Pn-1=Wn-1+S, n is an integer larger than 1, Wn-1 represents a line width of the (n-1)th lead line, S represents a space between the adjacent lead lines, and the pitches P1˜Pn-1 of the plurality of lead lines are not completely the same.

A display substrate includes a pixel electrode disposed in a display area, a first pad part disposed in a first area of a peripheral area which is disposed adjacent to the display area, where the first pad part is electrically connected to a driver circuit, a second pad part disposed in a second area of the peripheral area facing the first pad part, where the second pad part is electrically connected to a flexible circuit film which transfers a transmission signal to the driver circuit, and a connection line part disposed in an area between the first and second pad parts as a vertical line type, where the connection line part connects the first and second pad parts to each other.

A semiconductor device is composed of a power supply interconnection extending from a certain starting point in a first direction and also extending from the starting point in a second direction orthogonal to the first direction, a plurality of power pads, and connecting interconnections providing electrical connection between the power supply interconnection and the power pads. The power supply interconnection, the power pads, and the connecting interconnections are arranged in a symmetrical manner with respect to a symmetry line crossing the starting point and extending in a direction at an angle of 45 degree to the first and second directions.

The present invention discloses a system and method for reducing delay difference of differential transmission, a certain delay difference between waveforms of the P signal and N signal is generated through controlling delay adjustment to P signal or N signal of the differential signals and controlling delay adjustment value simultaneously, to compensate for the delay difference of differential transmission due to the channels. Therefore, the present invention can reduce the delay difference of differential transmission due to property discrepancy of board materials and delay inconsistency among pins of the connectors, and at same time simplify the scheme design.

A video encoding/decoding apparatus includes an encoding unit which processes video data to be transmitted in unit of slice, a multiplexer/demultiplexer which multiplexes the video data from the encoding unit and de-multiplexes video data received through a communication channel, a decoding unit which processes video data from the multiplexer/demultiplexer in unit of slice. The video information delay is reduced less than or equal to the audio information delay such that there is no need for additional memory to delay the audio information so as to synchronize with the video information.

Provided is a light receiving circuit, comprising four operational amplifiers, eight coupling resistors, an output triode, an auxiliary triode and a photodiode which are connected according to the scheme to respectively form a main line and an auxiliary line, wherein the main line is used for controlling the turn-on / turn-off of triodes; the auxiliary line is used for rapidly discharging the charge stored on the base electrode of the output triode. The invention provides a new light receiving circuit which has the performance of low transmission time delay; meanwhile, the light receiving circuit can reduce the delay difference between two voltage control signals through a second anti-phase amplifier, thereby optimizing output waveforms of the light receiving circuit.

The invention discloses a display panel and a display device and relates to the technical field of display. In the embodiment of the invention, by arranging first connecting lines A and first connecting lines B, namely when each first grid line is electrically connected with at least one first connecting line A transmitting grid electrode scanning signals and each second grid line is electricallyconnected with at least two first connecting line B transmitting same grid electrode scanning signals, the width of the first connecting lines A is set to be smaller than that of the first connectinglines B. Therefore, decrease of load difference of first grid lines and second grid lines can be facilitated, thus the delay difference of the first grid lines and the second grid lines is decreased,display of the display panel is more uniform, and accordingly the display effect of the display panel is improved.

A method and system of transmitting messages include requesting to submit a first request for transmitting a first message and to submit a second request for transmitting a second message until there is no first collision detected between the submitted first and second requests upon receipt of the submitted first and second requests. Before there is no first collision detected between the submitted first and second requests, it is requested to submit a third request for transmitting a third message and to submit a fourth request for transmitting a fourth message. However, requesting to re-submit the third request for transmitting the third message and to re-submit the fourth request for transmitting the fourth message if a second collision is detected between the submitted third and the second requests upon receipt thereof is delayed until there is no first collision detected between the submitted first and second requests.

The present disclosure relates to a centralized scheduling method and apparatus that considers non-uniform traffic and, more particularly, to a centralized scheduling method and apparatus for performing effective scheduling based on a characteristic of non-uniform traffic in consideration of a traffic distribution in a data center network.

A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.