37results about How to "Reduce latency variance" patented technology

A method is provided for equalizing latency among a group of connections that are being used by the same latency-sensitive application, such as for multi-player network gaming. Delay is added to the packet flow in each connection as necessary at the provider edge router connecting the application server to the network. An NMS connected to the provider edge router continuously monitors the round-trip delay of each connection, determines the additional delay of each connection required to equalize the delays, and informs the provider edge router. The provider edge router buffers traffic on each connection for the respective duration as indicated by the NMS. The NMS may also reroute some of the connections over higher latency resources to reduce the amount of buffering required, which provides the additional advantage of using what might otherwise be less used or economically less valued resources.

The invention discloses a lead wire structure and a displaying panel possessing the lead wire structure, comprising a displaying zone and a non-displaying zone. The displaying panel comprises a pixel array, at least one driving device and a plurality of lead wires. The pixel array is located in the displaying zone, and the driving device and the lead wires are located in the non-displaying zone; the lead wires are in electrical connections with the pixel array and the driving device, and are arranged as a fan-shaped structure between the pixel array and the driving device. Especially, the wire distance P<n-1> between the No.(n-1) lead wire and the No. n lead wire is equal to (W<n-1>+S), wherein, the n is a positive integer greater than 1, the W<n-1> represents the wire width of the No.(n-1) lead wire, and the S represents the clearance of adjacent lead wires; wherein, the wire distances P<1> to P<n-1> of the lead wires in the fan-shaped structure are not completely equal.

A semiconductor device is composed of a power supply interconnection extending from a certain starting point in a first direction and also extending from the starting point in a second direction orthogonal to the first direction, a plurality of power pads, and connecting interconnections providing electrical connection between the power supply interconnection and the power pads. The power supply interconnection, the power pads, and the connecting interconnections are arranged in a symmetrical manner with respect to a symmetry line crossing the starting point and extending in a direction at an angle of 45 degree to the first and second directions.

A delay synchronization loop type clock signal generating circuit includes: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring-type shift register for setting the delay time length of the digital delay line by flip-flop output of each stage thereof; and a delay amount control unit for controlling supply of shift clocks to the ring-type shift register, based on phase relation between the first clock signal and the second clock signal.

A complementary signal generating circuit according to an embodiment of the present invention includes: an inverting element inverting a first signal to generate a second signal; a first transistor connecting a first power supply potential and a first output terminal electrically in accordance with the first signal; a second transistor connecting the first output terminal and a second power supply potential electrically in accordance with the second signal; a third transistor connecting the first power supply potential and a second output terminal electrically in accordance with the second signal; and a fourth transistor connecting the second output terminal and the second power supply potential electrically in accordance with the first signal.

A delay synchronization loop type clock signal generating circuit includes: a delay line for delaying a first clock signal by a set delay amount and outputting; a delay time length setting unit for setting a delay time length of the delay line, based on phase difference between a second clock signal output from an output terminal and the first clock signal; a phase relation determining unit for determining whether or not the phase relation of the first clock signal and the second clock signal are in a particular phase relation; and a phase inversion / non-inversion unit for performing phase inversion of the first clock signal on a transmission path including the delay line, at the time of detecting the particular phase relation.

A liquid crystal display device includes a first substrate which comprises a plurality of pixels where a thin film transistor and a pixel electrode electrically connected to the thin film transistor are formed, the first substrate including a gate line and a data line which insulatingly intersect each other; and a gate driver which applies a gate driving signal to the gate line, the thin film transistor including a gate electrode which is connected to the gate line; a source electrode which is connected to the data line; and a drain electrode which is connected to the pixel electrode, and the pixels being decreased in a value of Cp / (Cp+Clc+Cst) as going toward the gate driver (where, Cp: a sum of parasitic capacity between the gate electrode and the source electrode and parasitic capacity between the gate electrode and the drain electrode, Clc: liquid crystal capacity, and Cst: storage capacity).

Embodiments of the present invention provide a display panel and a display device, which relate to the field of display technology and can reduce the delay difference between the output signal of the effective GOA unit and the output signal of the Dummy GOA unit; in the display panel, the gate drive circuit includes: The set multi-level effective shift register, and the virtual shift register after the last effective shift register; the multi-level effective shift register is connected with multiple gate lines; the clock signal line in the display panel includes: an effective clock signal line and the virtual clock signal line; the effective clock signal line is connected to the virtual clock signal through the connection control circuit; the connection control circuit is configured to: before the output scanning signal of the last effective shift register, control the effective clock signal line and the virtual clock signal The lines are disconnected; and under the control of the scanning signal output by the last effective shift register, the electrical connection between the effective clock signal line and the virtual clock signal line is controlled.

The present application discloses a displacement filling method and a related device, the method comprising: at t n‑2 moment, t n‑1 moment and t n The vehicle is recognized as the second vehicle by the point cloud of the first vehicle at all times; the t corresponding to the identification of the second vehicle n Time point cloud data to obtain the relative displacement s between the second vehicle and the first vehicle n ;according to the relative displacement s n and fill in the displacement Δs to obtain the actual relative displacement s between the second vehicle and the first vehicle n ’; filling displacement Δs is based on the corresponding t of the second vehicle n‑2 Time point cloud data, t n‑1 The relative displacement s between the second vehicle and the first vehicle obtained by point cloud data recognition at each moment n‑2 , relative velocity v n‑2 , relative displacement s n‑1 and the relative velocity v n‑1 obtained by the operation. It can be seen that based on the relative displacement s n‑2 , relative velocity v n‑2 , relative displacement s n‑1 and the relative velocity v n‑1 , pre-computing t n The filling displacement Δs that needs to be filled after point cloud data recognition at any time, using its relative displacement s n The actual relative displacement s obtained by filling n ’, reduce the delay difference and avoid the problem of inaccurate lag.

The present disclosure relates to a centralized scheduling method and apparatus that considers non-uniform traffic and, more particularly, to a centralized scheduling method and apparatus for performing effective scheduling based on a characteristic of non-uniform traffic in consideration of a traffic distribution in a data center network.

A light receiving circuit is composed of 4 operational amplifiers, 8 matching resistors, output transistors, auxiliary transistors and photodiodes; after the aforementioned components are connected according to the scheme of the present invention, a main circuit and an auxiliary circuit are respectively formed, and the main circuit is used for Control the on / off of the output triode, and the auxiliary circuit is used to quickly discharge the charge stored on the base of the output triode; the beneficial technical effect of the present invention is: a light receiving circuit with a new structure is proposed, the light receiving circuit It has the performance of low transmission delay time, and at the same time, the light receiving circuit can also reduce the delay difference between the two voltage control signals through the second inverting amplifier, so that the output waveform of the light receiving circuit can be optimized.