Improved method for verification by adopting reactive slave

Abstract

The invention discloses an improved method for verification by adopting reactive slave, which comprises the following steps of: building a UVM (Universal Verification Model) verification platform, and creating an excitation component, a transmission component and a reference model component; writing input excitation in the excitation assembly, and sending the input excitation to the interface assembly and the reference model assembly by the excitation assembly; the tested device obtains and processes the input excitation to obtain a signal result; the tested device outputs a signal result to the interface assembly; the transmission component obtains and encapsulates the signal result in the interface component to obtain transaction information; the transmission component broadcasts transaction information to the reference model component; the reference model component processes the transaction information and the input excitation to obtain a response result; the reference model component configures and starts a response sequence, and transmits a response result to the interface component; and the interface assembly outputs a response result to the tested device. According to the method, the tested device can be perfectly verified, the verification path is simpler, and the reusability of the verification environment is improved while the verification quality is improved.

Description

technical field [0001] The invention relates to the technical field of chip verification, in particular to an improved method for verification using a reactive slave. Background technique [0002] In the existing technology, such as figure 1 As shown, the req, rslt and rsp interfaces are usually packaged into req_agent components, rslt_agent components, and rsp_agent components respectively, and they work in active, passive and active modes respectively; first, the req_agent component works in active mode, and the user writes req_agent The sequence input stimulus of the component sends the input stimulus to the interface interface through the sequencer and driver of the req_agent component, and then the DUT (Device Under Test, device under test) performs calculations based on the input stimulus and outputs the signal result to the interface interface. At the same time, the monitor in req_agent will broadcast the input stimulus to the reference model to calculate the expecte...

AI Technical Summary

Problems solved by technology

[0003] However, the existing technology has the defect of poor reusability. The monitor in the rslt_agent component needs to communicate with the sequencer in the rsp_agent component in the verification environment, and the rsp_agent component needs to implement part of the logic for generating reactive slave sequences. The above will lead to logic division Unclear, so that the rslt_agent component and the rsp_agent component cannot be effectively packaged into independent packages, which will adversely affect the reusability of the verification environment

Images