Device for improving security of cache data of host and cache data reading and writing method and device
A technology for caching data and hosts, applied in the field of data security, which can solve the problems of user data leakage security risks, mapping table information is easy to be analyzed and cracked, and achieve the effect of reducing the risk of being leaked and improving security
Active Publication Date: 2022-03-01
绿晶半导体科技(北京)有限公司
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- Claims
- Application Information
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Problems solved by technology
However, under normal circumstances, the mapping table data is stored in plain code in the host-side HMB cache, which makes the mapping table information easy to be analyzed and cracked, thus causing a great security risk to the leakage of user data
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[0043] Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures indicate functionally identical or similar elements. While various aspects of the embodiments are shown in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
[0044] The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.
[0045] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific implementation manners. It will be understood by those skilled in the art that the present application may be practiced without certain of the specific details. In some instances, methods, means, co...
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The invention relates to a device for improving security of host cache data. The device comprises a transmission control unit, a verification module and an encryption and decryption module, the transmission control unit, the verification module and the encryption and decryption module are all suitable for being loaded in a storage hard disk which performs data interaction with a host cache; wherein the transmission control unit, the verification module and the encryption and decryption module are electrically connected in sequence; the transmission control unit is suitable for being in communication connection with an on-chip cache module in the storage hard disk and is configured to perform data transmission and exchange between the storage hard disk and a host cache; the verification module is configured to verify data transmitted between the storage hard disk and the host cache; and the encryption and decryption module is configured to encrypt the data written into the host cache by the storage hard disk and decrypt the data read into the storage hard disk by the host cache. According to the method, the situation that the on-chip cache data is analyzed and cracked after being stored in the host cache is effectively prevented, and the risk that the user data is leaked is greatly reduced.
Description
technical field [0001] The present application relates to the technical field of data security, and in particular to a device for improving the security of cached data in a host, and a method and device for reading and writing cached data. Background technique [0002] The full name of HMB is Host Memory Buffer, which is the host memory cache technology, which enables SSD (Solid State Drive) to improve the performance of SSD itself with the help of DRAM (Dynamic Random Access Memory) and the high-speed read and write characteristics of host-side memory. Achieve performance comparable to SSDs with built-in DRAM. When an NVMe SSD that supports the HMB function reads and writes, it will automatically start this function for performance improvement and optimization. The principle of the HMB technology is to reserve a cache area in the host memory for SSD use. This part of the area only occupies a small part of the PC memory, and the memory reserves sufficient space to coordinat...
Claims
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Login to View More IPC IPC(8): G06F21/60G06F3/06
CPCG06F21/602G06F21/606G06F3/062G06F3/0655G06F3/0674Y02D10/00
Inventor 巴书法滕向阳
Owner 绿晶半导体科技(北京)有限公司