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Multi-channel sampling time offset calibration module and time-interleaved analog-to-digital converter

A sampling time, calibration module technology, applied in the direction of analog-to-digital converter, analog-to-digital conversion, code conversion, etc., can solve the problem of sampling time deviation, sampling accuracy decline of multi-channel ADC sampling unit, etc.

Active Publication Date: 2022-05-20
SUTENG INNOVATION TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, there are sampling time deviations in multiple channels of the multi-channel ADC sampling unit, and the sampling time deviation will cause the sampling accuracy of the multi-channel ADC sampling unit to decrease

Method used

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  • Multi-channel sampling time offset calibration module and time-interleaved analog-to-digital converter
  • Multi-channel sampling time offset calibration module and time-interleaved analog-to-digital converter
  • Multi-channel sampling time offset calibration module and time-interleaved analog-to-digital converter

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Embodiment 1

[0063] The multi-channel time-interleaved analog-to-digital converter is a high-speed ADC (Analog-to-Digital Converter) architecture that connects multiple analog-to-digital converters in parallel and uses interleaved clocks to make them work alternately in a time-division multiplexing manner. The low-speed signal output by each sub-channel ADC module working at low frequency is combined into a high-speed signal for increasing the sampling rate.

[0064] refer to figure 1 As shown, in the related art, the multi-channel time-interleaved analog-to-digital converter includes multiple ADC units; the multiple ADC units have the same structure, work alternately under the control of multi-phase sampling clock signals CLK_Φ1, CLK_Φ2...CLK_ΦM, and input analog signals x(t) is converted into a digital signal y(n), M is a positive integer, and M≥2.

[0065] Exemplarily, figure 2 Ideally, the timing diagram of the reference clock signal CLK_ref and the multi-phase sampling clock signal...

Embodiment 2

[0133] Such as Figure 16 As shown, the difference between this embodiment and the first embodiment is that the comparator 121 is not multiplexed in the sub-channel ADC module 300 , and the comparator 121 is only used in the multi-channel sampling time offset calibration unit 100 .

[0134] In this embodiment, when the multi-channel time-interleaved analog-to-digital converter is in the normal working mode, the two input terminals of the multiple sub-channel ADC modules 300 respectively receive the analog signals Vip and Vin, and the multi-phase sampling clock signals VDL_Φ1, VDL_Φ2 ...under the control of VDL_ΦM, the analog signals Vip and Vin are converted into digital signals and sent to the data selection module 400; when the multi-channel time-interleaved analog-to-digital converter is in the calibration mode, the multiple detection units 120 are in the calibration enable signal CAL_en_delay Detection of multiple time intervals Δt under control 1_ref , Δt 2_ref …Δt M_r...

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Abstract

This application discloses a multi-channel sampling time deviation calibration module and a time-interleaved analog-to-digital converter. The multi-channel sampling time deviation calibration module includes multiple delay controllable units, multiple detection units, and delay control units; multiple delays can be The input terminal of the control unit receives one-to-one corresponding multi-phase sampling clock signal, and the output terminal is connected with the input terminals of multiple detection units in one-to-one correspondence; the output terminals of multiple detection units are connected with the input terminals of the delay control unit in one-to-one correspondence ; The output end of the delay control unit is connected to the input ends of a plurality of delay controllable units in one-to-one correspondence; the application detects multiple time detections corresponding to the multi-phase sampling clock signal one-to-one through the detection time window, and according to the detection results Counting is performed, and the delays of multiple delay controllable units are adjusted by using the counting results, so that the difference between the count values ​​of the first signs output by any two detection units is within a preset range, and the calibration of the sampling time deviation is realized.

Description

technical field [0001] The present application relates to the technical field of analog-to-digital conversion, in particular to a multi-channel sampling time offset calibration module and a time-interleaved analog-to-digital converter. Background technique [0002] At present, in order to increase the sampling rate of the ADC sampling unit, multi-phase sampling clock signals are used in the related art to control the multi-channel ADC sampling units to work alternately in a time-interleaved manner. [0003] When the ADC units of each channel in the multi-channel ADC sampling unit are identical, the sampling rate of the multiple ADC sampling units is proportional to the number of interleaved parallel ADC channels. That is, it is assumed that multiple ADC sampling units use M ADC sampling units of the same type to complete sampling alternately in sequence, and M is a positive integer greater than or equal to 2; the sampling rate of multiple ADC sampling units can reach M times...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/10H03M1/12
CPCH03M1/1023H03M1/1245H03M1/1215
Inventor 臧军领刘佳
Owner SUTENG INNOVATION TECH CO LTD
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