Convolution operation hardware accelerator and data processing method

A hardware accelerator and convolution operation technology, applied in the fields of electrical digital data processing, complex mathematical operations, instruments, etc., can solve the problem of low calculation efficiency, difficulty in making full use of hardware accelerator calculation resources, and inability to efficiently support convolution of different sizes Computing and other issues to achieve the effects of efficient output, versatility improvement, and efficient input

Pending Publication Date: 2022-04-12
HANGZHOU FEISHU TECH CO LTD
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Problems solved by technology

[0003] In the existing technology, the versatility of the convolution operation is not flexible enough to efficiently support convolution operations of diff...

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  • Convolution operation hardware accelerator and data processing method
  • Convolution operation hardware accelerator and data processing method
  • Convolution operation hardware accelerator and data processing method

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Embodiment Construction

[0037] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings, but these embodiments do not limit the present invention, those of ordinary skill in the art make structural, method, or functional changes based on these embodiments All are included in the scope of protection of the present invention.

[0038] Such as figure 1 In one embodiment of the present invention shown, the present invention provides a hardware accelerator for convolution operation, including a feature map reorganization module 10, a feature map cache write control module 11, a feature map cache module 12, a feature map cache read control module 13, N convolution kernel cache modules 14 and N calculation modules 15, the feature map cache module includes M parallel feature map cache units, M and N are integers greater than or equal to 1, wherein,

[0039] The feature map reorganization module 10 is used to segment each row of i...

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Abstract

The invention discloses a convolution operation hardware accelerator which is characterized in that a feature graph recombination module segments each row of input feature data of an input feature graph, and each segment of data is M at most; the feature map cache write control module generates a feature map cache unit sequence number and a cache write address to be written into each piece of input feature data, the sequence number and the cache write address are written into the feature map cache module, and at most M pieces of input feature data are written into M feature map cache units in parallel in the same clock period; the feature map cache read control module reads at most M pieces of input feature data in parallel in a single clock period in one convolution operation; the convolution kernel cache module writes a convolution kernel of a single output channel into M convolution kernel cache units according to the fact that M pieces of convolution kernel data are taken as a group; and the calculation module performs corresponding convolution operation on the convolution kernel data and the input feature data. According to the invention, the hardware accelerator can support the convolution operation of different size parameters, and the calculation efficiency of the convolution operation is improved.

Description

technical field [0001] The present invention relates to the technical field of deep learning hardware acceleration, in particular to a convolution operation hardware accelerator and a data processing method. Background technique [0002] Convolutional neural network is one of the most important algorithms in deep learning, which is widely used in many fields such as target recognition, unmanned driving and artificial intelligence. The convolution operation is the most computationally intensive part of a convolutional neural network. As the current convolutional neural network is getting deeper and deeper, the amount of calculation is increasing, and the data size of each layer operator is variable, so the calculation efficiency improvement and calculation optimization of convolution operations have become urgent problems for hardware accelerators. . [0003] In the prior art, the versatility of the convolution operation is not flexible enough to efficiently support convolu...

Claims

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Application Information

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IPC IPC(8): G06N3/04G06F17/15G06F9/355
Inventor 丁昊杰王文华
Owner HANGZHOU FEISHU TECH CO LTD
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