Convolution operation hardware accelerator and data processing method

Abstract

The invention discloses a convolution operation hardware accelerator which is characterized in that a feature graph recombination module segments each row of input feature data of an input feature graph, and each segment of data is M at most; the feature map cache write control module generates a feature map cache unit sequence number and a cache write address to be written into each piece of input feature data, the sequence number and the cache write address are written into the feature map cache module, and at most M pieces of input feature data are written into M feature map cache units in parallel in the same clock period; the feature map cache read control module reads at most M pieces of input feature data in parallel in a single clock period in one convolution operation; the convolution kernel cache module writes a convolution kernel of a single output channel into M convolution kernel cache units according to the fact that M pieces of convolution kernel data are taken as a group; and the calculation module performs corresponding convolution operation on the convolution kernel data and the input feature data. According to the invention, the hardware accelerator can support the convolution operation of different size parameters, and the calculation efficiency of the convolution operation is improved.

Description

technical field [0001] The present invention relates to the technical field of deep learning hardware acceleration, in particular to a convolution operation hardware accelerator and a data processing method. Background technique [0002] Convolutional neural network is one of the most important algorithms in deep learning, which is widely used in many fields such as target recognition, unmanned driving and artificial intelligence. The convolution operation is the most computationally intensive part of a convolutional neural network. As the current convolutional neural network is getting deeper and deeper, the amount of calculation is increasing, and the data size of each layer operator is variable, so the calculation efficiency improvement and calculation optimization of convolution operations have become urgent problems for hardware accelerators. . [0003] In the prior art, the versatility of the convolution operation is not flexible enough to efficiently support convolu...

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Problems solved by technology

[0003] In the existing technology, the versatility of the convolution operation is not flexible enough to efficiently support convolution operations of different sizes, it is difficult to make full use of the computing resources on the hardware accelerator, and there is a technical problem of low computing efficiency

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