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Chip layout structure for improving anti-interference capability of LDO (low dropout regulator)

A layout structure and chip technology, applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve problems affecting chip stability and low PSRR, and achieve the effect of improving the ability to resist power supply interference

Active Publication Date: 2022-05-13
上海芯圣电子股份有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, if the LDO in the chip is disturbed by the external power supply, the PSRR will be relatively low, thus affecting the stability of the chip

Method used

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  • Chip layout structure for improving anti-interference capability of LDO (low dropout regulator)

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Embodiment Construction

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the following will combine the appended figure 1 , clearly and completely describe the technical solutions in the embodiments of the present invention, obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

[0031] Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall wit...

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Abstract

The invention discloses a chip layout structure, which is characterized in that the chip layout structure comprises at least one metal layer, an inductor is designed on each metal layer, and a VDD (Voltage Drain Drain) of a chip is connected to a power supply input end of an LDO (Low Dropout Regulator) in the chip through the metal layer. According to the chip layout structure, the power supply interference resistance of the LDO is improved by utilizing the inductor formed by the metal layer.

Description

technical field [0001] The invention belongs to the field of chips, in particular to a chip layout structure for improving the anti-interference ability of an LDO. LDO stands for Low Dropout Linear Regulator. Background technique [0002] The main reasons for using LDO in the chip are: LDO's low cost, low noise, and small quiescent current, these are its outstanding advantages. However, if the LDO in the chip is disturbed by an external power supply, the PSRR will be relatively low, thereby affecting the stability of the chip. [0003] There is an urgent need in the field for a chip layout structure that can improve the anti-interference ability of the LDO. Contents of the invention [0004] In view of this, the present invention proposes a chip layout structure, characterized in that: [0005] The chip layout structure includes at least one metal layer, wherein, [0006] Inductors are designed on each metal layer, [0007] The VDD of the chip is connected to the powe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/522H01L23/64H01L27/02
CPCH01L23/5227H01L23/645H01L27/0207
Inventor 袁少华王铭义马洋
Owner 上海芯圣电子股份有限公司
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