Punch-through gate co-implant species for controlling dopant distribution in transistors

Abstract

In described examples, an integrated circuit (IC) includes a metal oxide semiconductor (MOS) transistor (100) formed in a semiconductor substrate (106). A transistor (100) includes a gate structure (104) formed over a surface of the substrate (106) and source and drain regions of a first conductivity type formed in the substrate on both sides of the gate structure (104). A well region (112) having a second opposite conductivity type is between the source and drain regions under the gate structure (104). The well region (112) includes a well dopant and a punch-through gate co-implant species. The well dopant and the co-implant species have a reverse distribution extending from the surface of the substrate (106) into the well region (112).

Description

technical field [0001] The present description relates to transistors and methods of making transistors with through-gate co-implantation species implantation to control dopant profiles. Background technique [0002] During device fabrication on a die, mismatches can occur locally and globally between device parameters. For example, transistor mismatch can occur in variability in threshold voltage, maximum transconductance, and drain current. As one example, variability in doping profiles can affect transistor mismatch. A common approach to improving mismatch is to increase the area (eg, width and / or length) of the transistor devices on the die. However, this approach results in larger devices and reduces device density on the die. Therefore, there is a need for a method of improving mismatch that also allows for smaller devices and increases the device density of integrated circuits. SUMMARY OF THE INVENTION [0003] In the described example, an integrated circuit (IC...

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However, this approach results in larger devices and reduces device density on the die

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