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High frequency clock signal distribution utilizing CMOS negative impedance terminations

A clock signal, high-frequency clock technology, applied in the direction of generating/distributing signals, automatic power control, semiconductor devices, etc., can solve problems such as influence

Inactive Publication Date: 2004-07-21
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Many prior art methods for clock distribution suffer due to distortion or delay at the rising edge of the clock signal

Method used

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  • High frequency clock signal distribution utilizing CMOS negative impedance terminations
  • High frequency clock signal distribution utilizing CMOS negative impedance terminations
  • High frequency clock signal distribution utilizing CMOS negative impedance terminations

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Embodiment Construction

[0034] With reference now to the drawings and in particular to figure 1 , which describes a clock signal distribution system using a two-conductor transmission line. This two-conductor transmission line conducts the clock signal throughout the integrated circuit 8 . The clock signal and the clock signal complement are simultaneously distributed across the differential transmission line 26 .

[0035] In a preferred embodiment, the clock signal and the clock signal complement are identical in form, however, the clock signal complement is shifted in phase by 180 degrees relative to the clock signal. The differential clock implementation circuit ensures low noise throughout the integrated circuit 8 .

[0036] The differential clock system of the present invention can compensate for clock signal attenuation by using negative impedance terminations. Use the complement of the clock signal to trigger or cause a negative impedance on the clock signal.

[0037] Typically, a precisio...

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Abstract

A system for synchronizing circuit operation within an integrated circuit having a high frequency clock is disclosed. The system includes an oscillator for providing a clock signal and a clock signal complement. A two conductor transmission line is utilized to distribute the clock signal. The two conductor transmission line has a first conductor coupled to the clock signal, a second conductor coupled to the clock signal complement and sub-circuits providing the integrated circuit with a differential clock signal. Negative impedance transmission line terminations are then attached in parallel with the transmission line. The terminations boost the clock signal transition times and the clock signal complement transition times to provide high frequency circuit synchronization within the integrated circuit.

Description

technical field [0001] In general, the present invention relates to clock signal distribution within integrated circuits, and more particularly to a differential clock signal distribution system. More particularly, the present invention relates to a differential clock signal distribution network using negative impedance termination. Background technique [0002] Synchronization of logic circuits within integrated circuits is accomplished by distributing a master clock signal to each timing critical circuit. Proper operation of an information processing unit such as a microprocessor requires all digital signals to be in a stable state when data is clocked. In all "timekeeping" systems there is a master clock that controls data transmission. [0003] An oscillator and a central buffer are typically used in integrated circuits to generate and amplify clock signals for distribution to digital subcircuits. The interconnection of subcircuits that are not connected to an integra...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/10H01L21/822H01L21/8238H01L27/04H01L27/092
CPCG06F1/10
Inventor U·S·高沙尔
Owner INT BUSINESS MASCH CORP