Data processing device and its data read method

Abstract

A data processing apparatus has a main memory having a plurality of successive memory spaces with a series of main addresses assigned thereto and a plurality of memory banks having a plurality of successive memory spaces with a series of bank addresses assigned commonly thereto. A bank switching instruction designating a particular bank address of the first memory bank is stored in an arbitrary memory space in the main memory. First through (n-1)th memory banks each have a virtual space where no stored data is present in respective final bank address thereof. A main return instruction designating a particular main address of the main memory is stored in the memory address represented by a particular bank address of the nth memory bank. Stored data in the main memory is read successively from the main addresses beginning with a head address. When the bank switching instruction is read, the readout destination is branched to the first memory bank. Data stored in the first memory bank, the second memory bank, and the nth memory bank are successively read. When the main return instruction is read from the nth memory bank, the readout destination returns to the main memory, and data is read from a particular main address of the main memory.

Description

technical field [0001] The invention relates to a data processing device having a main memory and a plurality of memory blocks. Background technique [0002] A conventional data processing device will refer to the accompanying drawings figure 1 and figure 2 Described below. like figure 1 As shown, this data processing device includes a main memory 101, n storage blocks 102 1 to 102 n , a CPU (Central Processing Unit) 103, and a register circuit 104. [0003] The main memory 101 has many continuous storage spaces, and each storage space has a sequence of main addresses from "000", "001", . . . up to "010" set therefor. storage block 102 1 to 102 n There are also multiple continuous storage spaces, and the storage space of each storage block has a common continuous block address "011", "012", ... until "100" set therefor. CPU103 communicates with main memory 101 and storage block 102 through address bus 105 and a data bus (not marked on the figure) 1 The data stored...

AI Technical Summary

Problems solved by technology

The process of setting from the first to the nth main return instruction in the end block address is complicated

[0012] In addition, relatively long continuous data cannot be stored in the main memory 101, because the conversion instruction from the first to the nth block is stored in any main address

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