Flip-flop circuit

Abstract

In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced. In FIG. 1, an output signal of an inverter circuit (INV1) constituting a latch circuit (2) connected to the output terminal of an input section (1) is used as an input signal of a control section (3). Thus, a control signal output from the control section (3) to the input section (1) is stabilized, thereby suppressing unnecessary operation of circuit elements and reducing unnecessary power consumption. In addition, the configuration of the control section (3) is simplified. As a result, the number of transistors constituting the circuit and the circuit area can be reduced.

Description

technical field [0001] The invention relates to a flip-flop circuit with high-speed action, in particular to a flip-flop circuit with few transistors and low power consumption. Background technique [0002] In general, among logic circuits in semiconductor integrated circuits, flip-flop circuits have a large influence on area, power consumption, and critical path delay, and it is desired to reduce the area, power consumption, and speed of flip-flop circuits. [0003] Conventionally, for high-speed applications, there is a flip-flop circuit using a latch circuit that performs data access during a pulse width period shorter than a clock cycle. Hereinafter, a prior art example of a flip-flop circuit having such a configuration will be described. [0004] Figure 13 A configuration example of a flip-flop circuit called SDFF (Semi-Dynamic Flip-Flop) is shown. [0005] exist Figure 13 Among them, D represents an input terminal, CK represents a clock terminal, and Q represents a...

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Problems solved by technology

In this way, in Figure 13 of prior art circuits that contain circuits that dissipate power as

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