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Multi master controller single chip implement method for high speed peripheral component interconnection bus

A technology of external input and PCI bus, which is applied in the direction of instrumentation, electrical digital data processing, etc., and can solve the problem that the bus interface is difficult to meet the system requirements, etc.

Inactive Publication Date: 2006-09-27
BEIJING HAPPOK INFORMATION TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This is because the high-speed multi-PCI Master interface controller is difficult to meet the system requirements in the timing of the bus interface, and its design is very challenging.

Method used

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  • Multi master controller single chip implement method for high speed peripheral component interconnection bus
  • Multi master controller single chip implement method for high speed peripheral component interconnection bus
  • Multi master controller single chip implement method for high speed peripheral component interconnection bus

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0045] Example 1 PCI Master state machine

[0046] parameter S0=0, S1=1, S2=2, S3=3,

[0047] S4=4, S5=5, S6=6, S7=7;

[0048] reg[2:0]Q_MS, D_MS;

[0049] always@(posedge CLKI or posedge RESET)begin

[0050] if(RESET)Q_MS=S0;

[0051] else Q_MS=#10D_MS;

[0052] end

[0053] / / The time of signal GNT_I is critical

[0054] always @(Q_MS or REQ_Td or GNT_I or FRAME_I or IRDY_I

[0055] or TRDY_I or STOP_I or Request or DEV_TO)begin

[0056] D_MS=Q_MS;

[0057] case(Q_MS) / / synopsys parallel_case full_case

[0058] S0: begin

[0059] if(!REQ_Td & !GNT_I & FRAME_I & IRDY_I)

[0060] D_MS=S1;

[0061] else if(REQ_Td & !GNT_I & FRAME_I &IRDY_I)

[0062] D_MS=S5;

[0063] end

[0064] S1: begin

[0065] D_MS=S3;

[0066] end ...

example 2

[0089] Example 2 PCI Master state machine realized by key path extraction method

[0090] parameter S0=0, S1=1, S2=2, S3=3,

[0091] S4=4, S5=5, S6=6, S7=7;

[0092] reg[2:0]Q_MS,D_MS;

[0093] always @(posedge CLKI or posedge RESET)begin

[0094] if(RESET)Q_MS=S0;

[0095] else Q_MS=#10 D_MS;

[0096] end

[0097] / * abstract the signals which have more setup time to

[0098] generate logic first * /

[0099] / / output the P_MS to module port

[0100] reg[2:0]P_MS;

[0101] always @(Q_MS or REQ_Td or FRAME_I or IRDY_I

[0102] or TRDY_I or STOP_I or DEV_TO or Request)begin

[0103] P_MS=Q_MS;

[0104] case(P_MS) / / synopsys parallel_case full_case

[0105] S0: begin

[0106] if(!REQ_Td & FRAME_I & IRDY_I)

[0107] P_MS=S1;

[0108] else if(REQ_Td & FRAME_I & IRDY_I)

[0109] P_M...

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Abstract

The present invention relates to bus single-chip sub-system technology, and includes the method of extracting key signal path from complex state computer and single-chip realized high speed PCI bus multi-master controller. The present invention includes the following steps: the first step of determining one key signal based on the time requirement and arrival time of outer input excitation signal of the PCI bus master controller state machine; the second step of substituting the condition judgment or logic value of the two values, '0' and '1', of the key signal to original state machine to obtain the intermediate state variable; and the third step of substituting the key signal as the unique outer input signal of the final state machine and the intermediate state variable as the value assignment for the final state machine to original state machine and the final state machine. The said method can solve the key signal path problem in PCI bus multi-master chip design.

Description

technical field [0001] The present invention relates to the technical field of SoC (System on a Chip, system on a chip) chip design, single-chip subsystem based on PCI (Peripheral Component Interconnection, peripheral component interconnection) bus, particularly a kind of multi-master control of high-speed PCI bus Device (Master) single chip implementation method. Background technique [0002] As software and hardware become increasingly complex, the specification of the PCI bus becomes more and more stringent for various IPs (Intelligent Property, intellectual property rights) based on the PCI bus. PCI has a powerful interconnection capability and is specially used to connect various high-performance peripheral devices, such as graphics processors, full-motion video processors, SCSI (Small Computer System Interface, small computer system interface) and LAN (Local Area Network, local area network ) and other interface cards. For SoC designers, it is a very good solution to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38
Inventor 张亮韩承德
Owner BEIJING HAPPOK INFORMATION TECH