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Semiconductor device with fraud structure

A semiconductor and device technology, applied in the field of semiconductor devices, can solve problems such as large parasitic capacitance, achieve the effect of uniform parasitic capacitance and prevent electrical failure

Inactive Publication Date: 2006-10-18
FUJITSU SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This parasitic capacitance is relatively large because the pseudo local interconnect LID is connected to multiple subordinate pseudo structures

Method used

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  • Semiconductor device with fraud structure
  • Semiconductor device with fraud structure
  • Semiconductor device with fraud structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0032] Embodiments of the present invention will be described below with reference to the drawings.

[0033] figure 1 A plan layout of a semiconductor device according to an embodiment of the present invention is shown. Active regions AR(n) and AR(p) are bounded by isolation regions 4 formed by STI. Active region AR(p) for a p-channel MOS transistor is arranged in n-type well NW. A p-type well PW is arranged to surround this n-type well NW. Active region AR(n) for n-channel MOS transistors is arranged in p-type well PW. Dummy active regions 18 are arranged in n-type well NW and p-type well PW in such a manner that they do not lie across the boundary between n-type well NW and p-type well PW.

[0034]The gate electrode G is formed across the active region AR(n). A dummy gate electrode 19 is formed by using the same layer as that of the gate electrode G over each dummy active region 18 . The local interconnect LI is formed to interconnect desired regions of the semiconduc...

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PUM

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Abstract

The present invention provides a semiconductor device having: a semiconductor substrate having an isolation region defining a plurality of active regions; a gate electrode constituting a semiconductor element formed on each active region; an interstage covering the gate electrode an insulator; a local interconnect formed through the interlevel insulator and electrically connected to the semiconductor element; a dummy local interconnect formed through the interlevel insulator and electrically separated from the local interconnect; and a lower-level dummy structure, each of which includes a dummy active region, a dummy active region and a dummy gate electrode formed thereon, and a dummy gate electrode formed on the isolation region One of the electrodes, wherein each of the dummy local interconnects is not connected to two or more lower dummy structures.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly, to semiconductor devices having dummy structures that do not function as part of an electronic circuit. The dummy structure is composed of dummy active regions, dummy gate electrodes, dummy local interconnects and the like. Background technique [0002] Due to the high integration level of recent semiconductor integrated circuit devices, shallow trench isolation (STI, shallow trench isolation), which is beneficial to planarization, has been adopted as an isolation technology to replace local oxidation of silicon (LOCOS, local oxidation of silicon). Since the gate length becomes shorter than in the past, it is necessary to form the gate electrode with high patterning accuracy. Local interconnects are often used to electrically connect electronic components, such as MOS transistors and capacitors, in local areas. [0003] For example, a buffer silicon oxide film and a silico...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/52H01L27/06H01L21/76H01L21/3105H01L21/3205H01L21/762H01L21/768H01L21/82H01L21/822H01L21/8234H01L23/522H01L27/02H01L27/04H01L27/08H01L27/088
CPCH01L21/31053H01L21/76229H01L21/7684H01L21/76895H01L21/823437H01L21/823475H01L23/522H01L27/0207H01L2924/0002H01L2924/00H01L21/82
Inventor 南条亮太
Owner FUJITSU SEMICON LTD