A clock frequency multiplier circuit

Abstract

The invention discloses a clock frequency multiplier circuit comprising a frequency multiplier circuit base module and a time-delaying triggering portion, wherein the frequency multiplier circuit base module is the first stage of the frequency multiplier circuit, the frequency multiplier circuit base module provides frequency doubling signal input, output and rear stage time-delay triggering modular interface, the time-delay triggering module can make the lowering of the rear clock frequency doubling move backwards, thus achieving the effect of synchronization and broadening clock width.

Description

technical field [0001] The invention relates to a clock frequency multiplication circuit, in particular to a clock frequency multiplication circuit in circuit design and programmable logic device design. Background technique [0002] A clock multiplier circuit is a commonly used circuit in circuit design and programmable logic device design. [0003] In the existing circuit design and programmable logic device design, the implementation methods of the clock multiplier circuit are as follows: [0004] 1. Use another high-speed clock to sample and count the clock that needs to be multiplied, and output the multiplied clock. The disadvantage of this method is that, because the high-speed clock and the input clock are not synchronized, the phase relationship between the output clock and the input clock after frequency multiplication is uncertain. This frequency doubling method cannot be used in many occasions. At the same time, because another high-speed clock is required, th...

AI Technical Summary

Problems solved by technology

[0008] The technical problem solved by the present invention is to overcome the respective shortcomings in the clock frequency multiplication design in the prior art, and to solve the problem that the clock frequency multiplication in the prior art cannot simultaneously adapt to stability, constant phase, high compatibility, and low cost

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