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A clock frequency multiplier circuit

A frequency doubling circuit and clock frequency doubling technology, applied in electrical components, pulse processing, pulse technology, etc., can solve the problem that clock frequency doubling cannot be adapted to stability and low cost at the same time, achieve constant phase, simplify wiring requirements, and occupy resources less effect

Active Publication Date: 2004-12-29
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The technical problem solved by the present invention is to overcome the respective shortcomings in the clock frequency multiplication design in the prior art, and to solve the problem that the clock frequency multiplication in the prior art cannot simultaneously adapt to stability, constant phase, high compatibility, and low cost

Method used

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  • A clock frequency multiplier circuit
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Embodiment Construction

[0018] The specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings.

[0019] Such as figure 1 As shown, the clock frequency multiplication circuit of the present invention includes a frequency multiplication circuit basic module and a delay trigger part, the frequency multiplication circuit basic module is the first stage of the frequency multiplication circuit, and the delay trigger part is connected to the frequency multiplication circuit basic module in sequence , can be composed of one delay trigger module or multiple delay trigger modules connected in series.

[0020] The basic module of the frequency multiplication circuit provides the input and output of the frequency multiplication signal and the interface with the subsequent delay trigger module. The delay trigger part moves the position of the falling edge of the clock after frequency multiplication to achieve the effect of synch...

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Abstract

The invention discloses a clock frequency multiplier circuit comprising a frequency multiplier circuit base module and a time-delaying triggering portion, wherein the frequency multiplier circuit base module is the first stage of the frequency multiplier circuit, the frequency multiplier circuit base module provides frequency doubling signal input, output and rear stage time-delay triggering modular interface, the time-delay triggering module can make the lowering of the rear clock frequency doubling move backwards, thus achieving the effect of synchronization and broadening clock width.

Description

technical field [0001] The invention relates to a clock frequency multiplication circuit, in particular to a clock frequency multiplication circuit in circuit design and programmable logic device design. Background technique [0002] A clock multiplier circuit is a commonly used circuit in circuit design and programmable logic device design. [0003] In the existing circuit design and programmable logic device design, the implementation methods of the clock multiplier circuit are as follows: [0004] 1. Use another high-speed clock to sample and count the clock that needs to be multiplied, and output the multiplied clock. The disadvantage of this method is that, because the high-speed clock and the input clock are not synchronized, the phase relationship between the output clock and the input clock after frequency multiplication is uncertain. This frequency doubling method cannot be used in many occasions. At the same time, because another high-speed clock is required, th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/00
Inventor 张磊黄友珍
Owner ZTE CORP