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Circuit structure and signal encode method for decreasing number of interface signals for serial ATA separated physical layer

A serial, physical layer technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of occupying a large area, difficult to control the pass rate, the area of ​​the main control chip 12 is large, etc., to achieve the effect of reducing the signal

Inactive Publication Date: 2002-10-30
VIA TECH INC
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although such a structure can support serial ATA devices and parallel ATA devices at the same time, however, the serial ATA physical layer 123 needs to occupy a relatively large area because it is mainly composed of high-frequency analog circuits, and it is desired to integrate it into the main control In the chip 12, the area of ​​the main control chip 12 will be too large, and the pass rate of its production is difficult to control

Method used

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  • Circuit structure and signal encode method for decreasing number of interface signals for serial ATA separated physical layer
  • Circuit structure and signal encode method for decreasing number of interface signals for serial ATA separated physical layer
  • Circuit structure and signal encode method for decreasing number of interface signals for serial ATA separated physical layer

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Embodiment Construction

[0044] First, see figure 2 , is a circuit block diagram of a split physical layer chip in a preferred embodiment of the present invention. As shown in the figure, its main structure includes: a parallel serial converter (serialize / deserializer; SerDes), a phase locked loop (phase locked loop; PLL), at least one transmitter (transmitter) 405, at least one receiver A receiver 407 and at least one OOB signal detector 461 .

[0045]The components required for the tandem ATA physical layer under the framework of the present invention are designed in two chips according to the circuit characteristics. The separate physical layer chip 40 includes all high-frequency analog circuits, and the other physical layer circuits are digital. The main circuit is integrated in the storage media controller, such as the coder (8BlOBencoder) that converts the 8bits signal and control signal of parallel ATA into 10bits signal and converts the 10bits signal from serial ATA signal into 8bits signal ...

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Abstract

A circuit for decreasing the number of interface signals for discrete ATA physical layer is disclosed. Its discrete physical layer chip is composed of at least one serial / parallel converter, at leastone parallel / serial converter, at least one phase-locked loop, at least one transmitter, at least one receiver and at least one OOB signal detector. It features that the digital circuit is separated from analog circuit, the high-frequency analog circuit is integrated into said physical layer chip, and the digital circuit is integrated into memory controller.

Description

technical field [0001] The invention relates to a circuit structure of an ATA interface, in particular to a circuit structure capable of reducing the number of serial ATA separation physical layer interface signals. Background technique [0002] In recent years, due to the high development of information-related industries and people's increasing requirements for computing and transmission speeds of information products, the industry has been continuously devoting itself to the development of various transmission interface specifications. As far as storage interfaces are concerned, the earliest transmission rate is 16MBps ATA (Advanced Technology Attachment) interface, through continuous improvement, the ATA33 interface with a transmission rate of 33MBps (mega byte per second), the ATA66 interface with a transmission rate of 66MBps, and even the interface specifications such as ATA100 and ATA133, but because the above-mentioned interface specifications are based on Parallel ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/32
Inventor 江晋毅王泽贤
Owner VIA TECH INC
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