Circuit structure and signal encode method for decreasing number of interface signals for serial ATA separated physical layer

Abstract

The present invention relates to an ATA interface circuit, especially a circuit capable of reducing the number of serial ATA separated physical layer interface signals. The separated physical layer chip mainly includes at least one parallel-to-serial converter, At least one series-to-parallel converter, at least one phase-locked loop, at least one transmitter, at least one receiver, and at least one OOB signal detector, using a digital and analog separation structure to manufacture high-frequency analog circuits in a separate In the physical layer chip, the digital circuit part can be integrated in the storage media controller, thereby ensuring the production pass rate of the digital control chip, and using the characteristics of the interface signal itself and the characteristics of ten-bit data encoding to convert the control signal and state The signal is transmitted or encoded into the data signal as a multi-level signal, so as to reduce the number of interface signals required for the connection between the separate physical layer chip and the main control chip.

Description

technical field [0001] The invention relates to an ATA interface circuit, in particular to a circuit capable of reducing the number of serial ATA separated physical layer interface signals. Background technique [0002] In recent years, due to the high development of information-related industries and people's increasing requirements for computing and transmission speeds of information products, the industry has been continuously devoting itself to the development of various transmission interface specifications. As far as storage interfaces are concerned, the earliest transmission rate is 16MBps ATA (Advanced Technology Attachment) interface, through continuous improvement, it produces ATA33 interface with a transmission rate of 33MBps (mega byte per second), ATA66 interface with a transmission rate of 66MBps, and even interface specifications such as ATA100 and ATA133. However, the above-mentioned interface specifications are based on Parallel (parallel) data transmission ...

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Problems solved by technology

Although such a structure can support serial ATA devices and parallel ATA devices at the same time, however, the serial ATA physical layer 123 needs to occupy a relatively large area because it is mainly composed of high-frequency analog circuits, and it is desired to integrate it into the main control In the chip 12, the area of ​​the main control chip 12 will be too large, and the pass rate of its production is difficult to control

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