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Architecture of silicon/oxide/nitride/oxide/silicon parts possessing high dielectric substance

An oxide and nitride technology, applied in the field of silicon/oxide/nitride/oxide/silicon semiconductor architecture, can solve the problem of reducing the gate length of silicon nitride read-only memory cells

Inactive Publication Date: 2003-10-08
MACRONIX INT CO LTD
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Problems solved by technology

However, the above requirements will hinder the reduction of the gate length of the known silicon nitride read-only memory cell to meet the application of deep sub-micron.

Method used

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  • Architecture of silicon/oxide/nitride/oxide/silicon parts possessing high dielectric substance
  • Architecture of silicon/oxide/nitride/oxide/silicon parts possessing high dielectric substance
  • Architecture of silicon/oxide/nitride/oxide/silicon parts possessing high dielectric substance

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Embodiment Construction

[0025] The invention will be referred to in detail in the examples, and this example is illustrated in the figures. Wherever possible, the same drawing reference numbers are used in the drawings to designate the same or similar parts.

[0026] figure 2 It is a cross-sectional view of a silicon nitride read only memory (nitride only memory, NROM for short) device 30 according to a preferred embodiment of the present invention. Please refer to figure 2 The silicon nitride read only memory device 30 includes a silicon substrate 32 having a source region 34 , a drain region 36 and a channel region 36 therebetween. The silicon nitride ROM device 30 can be an N-type silicon nitride ROM or a P-type silicon nitride ROM. In one embodiment, the source region 34 and the drain region 36 are N-type regions and the channel region 38 is a P-type region. In another embodiment, the source region 34 and the drain region 36 are P-type regions and the channel region 38 is an N-type region. ...

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Abstract

A device architecture includes following parts: the source electrode region, the drain electrode region, and the substrate of the channel region between the source and the drain electrodes, as well as the oxide layer, the mitration layer, the second oxide layer and the grid structure in sequence on the channel region. There are no source / drain regions on the substrate, which is under the grid structure. At least one injecting point is located no the gap wall of the sidewall on the nitration layer near to the grid structure in order to inject electros into the nitration layer. The injection point is positioned on the junction between the channel and one of the source electrode region or the drain electrode region. The electric charges are stored in the part of the nitration layer under thegap wall of the sidewall.

Description

field of invention [0001] The present invention relates to a silicon / oxide / nitride / oxide / silicon (silicon-oxide-nitride-oxide-silicon, referred to as SONOS) semiconductor structure (component), and in particular to a silicon nitride only A silicon / oxide / nitride / oxide / silicon architecture in a read memory (nitride only memory, NROM for short) semiconductor device. Background technique [0002] figure 1 A silicon nitride read-only memory device 10 is known. Please refer to figure 1 , the silicon nitride read only memory device 10 includes a substrate 12, which has an N-type source region (n-type source region) 14, an N-type drain region (n-type drain region) 16 and a P-type channel region (p-type channel region) 18 . The silicon nitride ROM device 10 further includes an oxide / nitride / oxide (ONO) structure 28 formed on the channel region 18 , a portion of the source region 14 and a portion of the drain region 16 . The oxide / nitride / oxide structure 28 includes a first oxide...

Claims

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Application Information

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IPC IPC(8): H01L29/51H01L29/792
CPCH01L29/513H01L29/518H01L29/7923
Inventor 林宏穗邹年凯赖汉昭卢道政
Owner MACRONIX INT CO LTD
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