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Nonvolatile semiconductor storage apparatus

A non-volatile, storage device technology, applied in information storage, static memory, read-only memory, etc., can solve problems such as incomparable data

Inactive Publication Date: 2004-03-24
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This results in the inability to perform sensitive comparisons between reference cells and memory cells of individual blocks to read out data

Method used

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  • Nonvolatile semiconductor storage apparatus
  • Nonvolatile semiconductor storage apparatus
  • Nonvolatile semiconductor storage apparatus

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Embodiment Construction

[0034] The present invention is described below with reference to the accompanying drawings.

[0035] figure 2 is a block diagram of a core circuit and its peripheral circuits constituting the nonvolatile semiconductor memory device according to the present invention. exist figure 2 In , the same reference numerals as in FIG. 1 denote the same elements, and thus their descriptions are omitted.

[0036] figure 2 The non-volatile semiconductor storage device in , includes a plurality of blocks 51 to 54 , a control circuit 61 , a reference cell circuit 62 , a reference Y gate circuit 63 and a boost circuit 64 . Each block 51 to 54 includes a memory cell array 11 , a Y gate circuit 12 , a readout circuit 13 , a reference load circuit 71 , and a switch circuit 72 .

[0037] The control circuit 61 supplies signals to respective relevant parts to control the operations of the blocks 51 to 54 and the reference cell circuit 62 according to an operation mode designated among read oper...

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Abstract

A nonvolatile semiconductor memory device includes a plurality of blocks each having a memory cell array, a reference cell, a signal line that supplies a reference signal read from the reference cell to each of the plurality of blocks, a reference load circuit which is provided in each of the plurality of blocks, and exerts a load on the reference signal that is identical to a load imposed on data that is read from the memory cell array, and a sensing circuit which is provided in each of the plurality of blocks, and compares the data with the reference signal having the load imposed thereon by the reference load circuit so as to sense the data.

Description

[0001] This application claims priority from Japanese Patent Application No. 2002-268317 filed with the Japan Patent Office on September 13, 2002, which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates to a nonvolatile semiconductor storage device, and more particularly, the present invention relates to a nonvolatile semiconductor storage device in which a memory cell array is divided into a plurality of blocks. Background technique [0003] In a nonvolatile semiconductor memory device, when determining the level of data read from a data memory cell, a reference memory cell independent of the data memory cell is used as a reference. This reference memory cell is not part of the memory cell array, but a peripheral circuit part of the memory cell array. A storage device has a set of reference storage units. When the memory cell array is divided into a plurality of blocks, it is necessary to distribute the output of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/06G11C7/14G11C16/26G11C16/28
CPCG11C16/28G11C7/14G11C16/26
Inventor 槻馆美弘
Owner FUJITSU LTD