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Scaleable interconnect structure for parallel computing and parallel memory access

A technology of interconnect structure and memory, which is applied in computing, computer, digital computer components, etc.

Inactive Publication Date: 2004-04-14
INTERACTIC HLDG LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0001] A persistent problem in massively parallel computing systems is providing sufficient data flow to the processors

Method used

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  • Scaleable interconnect structure for parallel computing and parallel memory access
  • Scaleable interconnect structure for parallel computing and parallel memory access
  • Scaleable interconnect structure for parallel computing and parallel memory access

Examples

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Embodiment Construction

[0014] see figure 1 , which shows a schematic block diagram of a generic system 100 composed of components, including one or more network interconnection structures. In this example, the general system 100 includes a top switch 110 and a bottom switch 112 formed from a network interconnect structure. The term "network interconnect structure" may also refer to other interconnect structures. Other systems may include additional components formed by network interconnection structures. The general system 100 depicts various components that may be core components of a basic example system. Some embodiments also contain other components in addition to these core components. Other components may include, for example: 1) shared memory; 2) direct connection 130 between top switch and bottom switch; 3) direct connection 140 between bottom switch and I / O, and 4) connection between logic unit 114 and Concentrator between bottom switches 112.

[0015] The general purpose system 100 ha...

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Abstract

Multiple processors are capable of accessing the same data in parallel using several innovative techniques. First, several remote processors can request to read from the same data location and the requests can be fulfilled in overlapping time periods. Second, several processors can access a data item located at the same position, and can read, write, or perform multiple operations on the same data item overlapping times. Third, one data packet can be multicast to several locations and a plurality of packets can be multicast to a plurality of sets of target locations.

Description

Background technique [0001] A persistent problem in massively parallel computing systems is providing sufficient data flow to the processors. High-bandwidth and low-latency interconnect structures are described in US patents US5996020 and US6289021, which greatly improve the data flow in the network. What is needed is a system that fully implements this high-bandwidth, low-latency interconnect fabric by supporting parallel memory access and computation across the network. Contents of the invention [0002] Several innovative techniques are used to enable multiple processors to access the same data in parallel. First, several remote processors may request to read data from the same data location, and the requests may be satisfied in overlapping time periods. Second, several processors can access data items at the same location and can overlap to read, write, or perform multiple operations on the same data item. Third, one data packet can be multicast to several places, and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/173G06F15/16G06F15/177H04L12/56
CPCG06F15/17375
Inventor 约翰·赫斯科克·S·里德
Owner INTERACTIC HLDG LLC
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