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Managing processor architected state upon an interrupt

A processor and state technology, applied in the field of data processing, can solve the problem of overall performance reduction of the processor

Inactive Publication Date: 2004-06-16
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, saving and subsequently restoring the architectural state of a process by the processor's execution units results in delays in the execution of interrupted processes and interrupt handlers
This delay reduces the overall performance of the processor

Method used

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  • Managing processor architected state upon an interrupt
  • Managing processor architected state upon an interrupt
  • Managing processor architected state upon an interrupt

Examples

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Embodiment Construction

[0027] Referring now to FIG. 2, a high-level block diagram of an exemplary embodiment of a multiprocessor (MP) data processing system 201 is depicted. Although MP data processing system 201 is described as a symmetric multiprocessor (SMP), the present invention may be used with any MP data processing system known to those skilled in the art of computer architecture, including but not limited to non-uniform memory access ( NUMA) MP or cache-only memory architecture (CacheOnly Memory Architecture, COMA) MP.

[0028] In accordance with the present invention, MP data processing system 201 includes a plurality of processing units 200, depicted as processing units 200a through 200n, connected for communication via interconnect 222. In a preferred embodiment, it should be understood that each processing unit 200 in MP data processing system 201, including processing unit 200a and processing unit 200n, is similar or identical in architecture. Processing unit 200a is a single integrat...

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Abstract

A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow copy of the hard architected permits rapid saving of the hard architected state for the interrupted process, so that the architected state of a next process can be immediately stored in the processor.

Description

technical field [0001] The present invention generally relates to the field of data processing, and more particularly to an improved data processing system and method for handling interrupts. Background technique [0002] While executing a set of computer instructions, the processor is frequently interrupted. This interrupt may be caused by an interrupt or exception. [0003] An interrupt is an asynchronous interrupt event that is not associated with the instruction that was executing when the interrupt occurred. That is, interrupts are often caused by some event external to the processor, such as input from an input / output (I / O) device, a call to an operation from another processor, and the like. Other interrupts may be internally caused, for example, by the expiration of a timer controlling task switching. [0004] An exception is a synchronous event caused directly by the execution of the instruction that was executing when the exception occurred. That is, an exceptio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/46G01R31/3185G06F9/48G06F12/00G06F12/08
CPCG06F9/30116G06F9/3012G01R31/318536G06F9/3013G06F9/30101G06F9/462
Inventor 拉维·K·阿里米利罗伯特·A·卡格诺尼盖伊·L·格思里威廉·J·斯塔克
Owner INT BUSINESS MASCH CORP