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Semiconductor device

A technology of semiconductors and transistors, applied in the field of semiconductor devices, can solve the problems of LSI manufacturing costs and increased manufacturing days

Active Publication Date: 2004-10-13
SANYO ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the existing BiCMOS process, due to the large increase in the number of relative CMOS process steps, the manufacturing cost and manufacturing days of LSI are greatly increased.

Method used

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Embodiment Construction

[0011] A semiconductor device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. figure 1 and figure 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. figure 1 An N-channel MOS transistor 10, a P-channel MOS transistor 20, and a vertical NPN bipolar transistor (Vertical NPN BJT) 30 are shown, figure 2 A lateral NPN bipolar transistor (Lateral NPN BJT) 40 , a lateral PNP bipolar transistor (Lateral PNP BJT) 50 , and a vertical PNP bipolar transistor (Vertical PNP BJT) 60 are shown. These two types of MOS transistors and four types of bipolar transistors are formed in the same semiconductor substrate 1 .

[0012] Second, refer to figure 1 The structures and manufacturing methods of the N-channel MOS transistor 10 , the P-channel MOS transistor 20 , and the vertical NPN bipolar transistor 30 will be described in detail.

[0013] Field insu...

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PUM

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Abstract

This invention provides a BiCMOS semiconductor device, of which the number of steps of manufacturing process is reduced. In the surface of a semiconductor substrate (1) a first N well (3A) and a second N well (3B) are deeply formed. A first P well (4A) is formed in the first N well (3A) and a N channel type MOS transistor (10) is formed in the first P well (4A). The second N well (3B) is used as a collector of a vertical type NPN bipolar transistor (30). A second P well (4B) is formed in the second N well (3B). The second P well (4B) is formed simultaneously with the first P well (4A). The second P well (4B) is used as a base of the vertical type NPN bipolar transistor (30). N+ type emitter layer (31) and a P+ type base layer (32) of the vertical type NPN bipolar transistor (30) are formed in the surface of the second P well (4B).

Description

technical field [0001] The present invention relates to a semiconductor device, in particular to a semiconductor device in which a MOS transistor and a bipolar transistor are provided on the same semiconductor substrate. Background technique [0002] In recent years, analog-digital hybrid LSIs that integrate analog circuits and digital circuits are being developed. In this type of LSI, the analog circuit is mainly composed of bipolar transistors, and the digital circuit is composed of MOS transistors. When forming a MOS transistor and a bipolar transistor on the same semiconductor substrate, a BiCMOS process combining a bidirectional process and a CMOS process is generally used. [0003] In the existing BiCMOS process, due to the large increase in the number of steps relative to the CMOS process, the manufacturing cost and manufacturing days of the LSI are greatly increased. In contrast, Patent Document 1 describes a technique for reducing the number of steps by forming a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/331H01L21/8222H01L21/8224H01L21/8228H01L21/8248H01L21/8249H01L27/06H01L27/082H01L29/73H01L29/732H01L29/735
CPCH01L29/7322H01L21/8249H01L29/735H01L27/0623
Inventor 五嶋一智大古田敏幸谷口敏光
Owner SANYO ELECTRIC CO LTD
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