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Processor power management and bus optimization method

A power management and processor technology, applied in the direction of program loading/starting, program control devices, etc., can solve problems such as complicated boot procedures and prolonged system boot time

Active Publication Date: 2004-11-17
VIA TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, both of the above two programs need to execute the interruption and reconnection of the LDT bus
Repeated execution of the same action by the hardware will cause disadvantages such as prolonged system startup time and complicated startup procedures.

Method used

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  • Processor power management and bus optimization method
  • Processor power management and bus optimization method
  • Processor power management and bus optimization method

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Embodiment Construction

[0025] refer to image 3 , image 3 It is a diagram showing the architecture of a computer system with an LDT bus. As shown in the figure, there is an LDT bus 12 between the processor 10 and the north bridge 14 . Here, the processor is the K8 CPU manufactured by AMD as an example. There is another bus 16 between the north bridge 14 and the south bridge 18 . When the processor power management program and the bus optimization program are to be executed, the LDT bus 12 between the processor 10 and the north bridge 14 must perform interruption and reconnection actions. It is controlled by the level change of the signal LDTSTOP#. The level of the signal LDTSTOP# is the first level in the normal situation (take the high level as an example), when the south bridge pulls down the level of the signal LDTSTOP# to the second level (take the low level as an example), the It is called the assert signal LDTSTOP#, and when both the processor 10 and the north bridge 14 receive the asser...

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Abstract

The invention is a method for digest managing of processor power specification sheets and for optimization of bus. The bus operation band width and the frequency of the bus between the processor and the north bridge chip are set, following, the power managing setting of the north bridge and the south bridge chip are started, then, the output operation frequency and the operation voltage are outputted to adjust the change information to the south bridge chip, then, a bus interrupt signal is outputted by the south bridge chip to interrupt the bus between the processor and the north bridge, and a counting number of the counter is started, the processor adjust the operation frequency and voltage according to the change of the frequency and the operation voltage, when the counting number of the counter reach a set value, the south bridge output the bus connecting signal, and works with the above mentioned width and frequency, the processor works in another frequency and voltage according to the change information of the operation frequency and voltage.

Description

technical field [0001] The invention relates to a processor power management and bus optimization method, in particular to a processor power management and bus optimization method applied to an AMD K8 operating platform (platform). technical background [0002] The Legacy I / O bus structure is widely used in embedded systems due to its low cost and ease of implementation using established standard software and hardware standards. However, its maximum operating frequency is only about 66MHz. Therefore, a processor with an operating frequency above 500MHz must use a bus with a higher bandwidth and operating frequency. [0003] Lightning Data Transport I / O Bus (Lightning Data Transport, LDT, I / O Bus), also known as High Transport I / O Bus (Hyper Transport, HT, I / O Bus), meets the needs of current computer networks, communication systems and The high bandwidth requirements required by other embedded systems require a bus architecture that is flexible, scalable, and easy to use. ...

Claims

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Application Information

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IPC IPC(8): G06F9/445
Inventor 徐明椲
Owner VIA TECH INC
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