Processor power management and bus optimization method

A power management and processor technology, applied in the direction of program loading/starting, program control devices, etc., can solve problems such as complicated boot procedures and prolonged system boot time
CN1547117AActive Publication Date: 2004-11-17VIA TECH INC
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Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
VIA TECH INC
Publication Date
2004-11-17

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Abstract

The invention is a method for digest managing of processor power specification sheets and for optimization of bus. The bus operation band width and the frequency of the bus between the processor and the north bridge chip are set, following, the power managing setting of the north bridge and the south bridge chip are started, then, the output operation frequency and the operation voltage are outputted to adjust the change information to the south bridge chip, then, a bus interrupt signal is outputted by the south bridge chip to interrupt the bus between the processor and the north bridge, and a counting number of the counter is started, the processor adjust the operation frequency and voltage according to the change of the frequency and the operation voltage, when the counting number of the counter reach a set value, the south bridge output the bus connecting signal, and works with the above mentioned width and frequency, the processor works in another frequency and voltage according to the change information of the operation frequency and voltage.
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Description

technical field

[0001] The invention relates to a processor power management and bus optimization method, in particular to a processor power management and bus optimization method applied to an AMD K8 operating platform (platform). technical background

[0002] The Legacy I / O bus structure is widely used in embedded systems due to its low cost and ease of implementation using established standard software and hardware standards. However, its maximum operating frequency is only about 66MHz. Therefore, a processor with an operating frequency above 500MHz must use a bus with a higher bandwidth and operating frequency.

[0003] Lightning Data Transport I / O Bus (Lightning Data Transport, LDT, I / O Bus), also known as High Transport I / O Bus (Hyper Transport, HT, I / O Bus), meets the needs of current computer networks, communication systems and The high bandwidth requirements required by other embedded systems require a bus architecture that is flexible, scalable, and easy to use. ...

Claims

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