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Galois field linear transformer

A Galois linear and linear transformation technology, applied in the field of Galois domain linear transformers, can solve problems such as period growth

Inactive Publication Date: 2005-01-26
ANALOG DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For systems using transmitters and receivers, the period will be doubled

Method used

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  • Galois field linear transformer
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Examples

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Embodiment Construction

[0018] figure 1 The shown prior art hardware wiring circuit for implementing the Galois field linear transformation circuit 10 includes two storage device flip-flop circuits 12 and 14 and two “exclusive OR” gates 16 and 18 . In this particular prior art implementation, two bit streams are provided, x bit stream input 20 to XOR gate 16 and y bit stream 22 provided as input to XOR gate 18 . The output from flip-flop circuit 12, designated A, provides an input to an exclusive OR gate 18. The second input is the y input on input 22 and the third input is output B of flip-flop circuit 14 . Output B of flip-flop circuit 14 also provides a second input to exclusive OR gate 16 .

[0019] After receiving a set of three bits on each of the x and y inputs in this particular example, circuit 10 will aim to determine the condition or output of flip-flop circuits 12 and 14 . Thus, the inputs of interest are x0 , x1 , x2 on input 20 and input bits y0 , y1 and y2 on y input line 22 . By p...

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Abstract

A Galois field linear transformer (28) includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix including a plurality of cells (40, 42, ... 70), each cell including an exclusive OR logic circuit (36) and AND logic circuit (34) having an output connected to the exclusive OR logic circuit and an input connected to one of the input bits and a programmable storage device (32) for providing an input to its associated AND logic circuit for setting the matrix to obtain a multi-cycle Galois field linear transfomation of the inputs in a single cycle.

Description

technical field [0001] The present invention relates to a Galois domain linear converter, in particular to such a Galois domain linear converter capable of realizing multi-period transformation within a single period. [0002] related application [0003] This application claims priority to Provisional Patent Application Serial No. 60 / 334,662, filed November 30,2001. technical background [0004] Conventional arithmetic logic circuits for error correction and detection, communication, encoding and decoding, and general bit processing can be implemented in hardware or software using Galois field linear transformations. Hardware implementations are expensive, require large amounts of chip space and power, and are generally not programmable. While software implementations avoid some of these disadvantages, software implementations have their own disadvantages. For example, a software implementation may require many instructions that process bits. Thus, for an implementation...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F5/00G06F7/00G06F7/72G09C1/00H03M13/01
CPCG06F7/724
Inventor 约瑟夫·斯坦海姆·普里莫乔舒亚·A·卡布罗特斯基
Owner ANALOG DEVICES INC