Semiconductor memory device

Abstract

A semiconductor memory device comprises a plurality of memory cell groups. Each memory cell group includes at least two memory cells. Each memory cell group includes a read section and a write section. The data of a memory cell is read from one bit line to a read global bit line through the read section. The write section is shared by at least two memory cells in the same memory cell group. Thus, writing of data in a memory cell is desirably achieved although the memory cell has a common 6-transistor structure.

Description

technical field [0001] The invention relates to a semiconductor storage device, in particular to a data writing method. Background technique [0002] Figure 8 The circuit shown is a conventional SRAM. In the figure, a plurality of memory cells 100 (only two are shown in the figure) are arranged in an array in the horizontal and vertical directions. Each memory cell 100 is connected to a word line WL and a pair of bit lines (BIT, NBIT). The structure of each memory unit 100 mentioned above is as follows: Figure 7 As shown, it consists of two load transistors MP1 and MP2 connected to a predetermined power supply VDD, two drive transistors MN1 and MN2 connected to a ground power supply VSS, and two conversion transistors MN3 and MN4. The gates of the two conversion transistors MN3 and MN4 are connected to the word line WL and the drains are connected to the pair of bit lines (BIT, NBIT). The above bit line pair (BIT, NBIT) such as Figure 8 As shown, it is connected to th...

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Problems solved by technology

[0007] But when Figure 9 In the shown semiconductor memory device, the number of constituent elements of the memory cell 900 is composed of 7 transistors compared with the usual 6-transistor memory cell. Since the number of transistors increases, there is a problem that the memory area increases.

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