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Command providing and controlling device and semiconductor device

A control device and semiconductor technology, applied in the fields of instruments, electrical digital data processing, etc., can solve the problems of reduced system processing efficiency, system errors, long time, etc., and achieve the effect of improving overall performance and ensuring successive and continuous effects.

Inactive Publication Date: 2005-02-23
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, if the right to use the bus is transferred to another host during the processing of the command group, it will take a long time for the host that issued the command group to obtain the processing result of the command group, and the processing efficiency of the entire system will decrease.
In addition, in the case where instructions are required to be executed continuously, a fatal system error may occur when the processing is interrupted

Method used

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  • Command providing and controlling device and semiconductor device
  • Command providing and controlling device and semiconductor device
  • Command providing and controlling device and semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0032] figure 1 It is a diagram showing a schematic configuration of a system including the command providing control device according to the first embodiment of the present invention. The command providing control device 10A according to the present embodiment appropriately selects a master granted the right to use the bus 30 among the hosts 20A and 20B, and supplies a command issued from the selected master to the bus 30 . Functional blocks 40A and 40B are connected to the bus 30 as slaves, and the masters 20A and 20B access the functional blocks 40A and 40B by granting the right to use the bus 30 by the command providing control device 10A. In addition, the bus 30 may be either an internal bus or an external bus. In addition, there may be any number of functional blocks connected to the internal bus 30 .

[0033] The command providing control device 10A includes: decoders 11A and 11B as command group end detection sections for detecting the end of the command group issue...

no. 2 Embodiment approach

[0048] Figure 4 It is a diagram showing a schematic configuration of a system including the command providing control device in the second embodiment of the present invention. The command provision control device 10B in this embodiment is also the same as the command provision control device 10A in the first embodiment, and appropriately selects the master using the bus 30 from the masters 20A and 20B, and provides the command issued by the selected master to the on bus 30. However, the command provision control device 10B differs from the command provision control device 10A in that it includes a buffer unit 13' having a FIFO 132' capable of storing commands issued by the hosts 20A and 20B, and an arbitration unit 12'. Hereinafter, only the points of difference from the command provision control device 10A will be described with respect to the command provision control device 10B.

[0049] Figure 5 A diagram showing the internal configuration of the command supply contro...

no. 3 Embodiment approach

[0058] Figure 6 A schematic configuration diagram showing a semiconductor device according to a third embodiment of the present invention. The semiconductor device 100 in this embodiment includes: the command providing control device 10A in the first embodiment; an internal master 20 such as a CPU (Central Processing Unit) and a DSP (Digital Signal Processor); an internal bus 30; and a function as a slave. blocks 40A and 40B; and an interface unit 50 for receiving commands from an external host. The command supply control device 10A, the function blocks 40A and 40B are connected to the internal bus 30 . In addition, external hosts 200A and 200B such as a CPU are connected to the interface unit 50 . in addition, Figure 6 The configuration of the semiconductor device 100 shown is just an example, and the number of internal hosts and functional blocks may be other than those shown in the figure. Meanwhile, the number of external hosts connected to the interface unit 50 may ...

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PUM

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Abstract

The invention applies a bus use right to a plurality of masters by an instruction group unit constituted of the bundle of instructions to be issued by each master. This instruction supply controller (10A) which appropriately selects one of a plurality of masters (20A, 20B) to which a bus use right should be applied, and supplies an instruction to be issued from the selected master to a bus (30) is provided with an instruction group end detecting parts (11A, 11B) to detect the end of an instruction group constituted of the bundle of instructions issued from the selected master and a mediating part (12) to apply the bus use right to the selected master until the end of the instruction group is detected by the instruction group end detecting parts (11A, 11B).

Description

technical field [0001] The present invention relates to an instruction providing control device for controlling the priority level of bus usage rights between multi-master processing devices (hereinafter referred to as "masters"), and particularly relates to sending a plurality of function blocks connected to one bus to two or more masters. Commands Commands applicable in this system provide priority control techniques. Background technique [0002] Regarding bus arbitration for a plurality of masters, conventionally, when bus priority is determined, a method of reducing the difference in execution time at the time of program execution is taken in consideration of an idle time during bus arbitration. Figure 10 It is a diagram of the configuration of the prioritization control device for the existing bus. According to this device, the cumulative value of the idle reserve period when the bus acquisition is arbitrated in each host 20-1 to 20-N is obtained through the first reg...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/36G06F13/00G06F13/362G06F13/364
CPCG06F13/364
Inventor 松井彻小谷敦
Owner PANASONIC CORP