Method for detecting periodic signal disorder

Abstract

The basic starting point of the invention is periodicity of periodic signal. Clock levels to be tested are sampled by using checking clock. Comparing levels at adjacent time determines whether signal to be tested is inordinate. Based on different requirement of precision for signal to be tested, electrical level values are compared at different times within a wider range. The invention guarantees the sampled points are in close vicinity to rising edges and falling edges of signal to be tested. Thus, the invention can detect lose of signal to be tested as well as detect change of duty ratio of signal to be tested. The method is easy to understand and easy to debug since the method is designed in hardware description language.

Description

Technical field [0001] The invention belongs to the field of electronic technology, and relates to a detection method for monitoring periodic signal disturbances by a high-frequency clock. Background technique [0002] In various systems such as communication and control, there are strict requirements for various periodic signals (such as clocks, frame headers, etc.). When the pulse is disordered (clock loss, duty cycle change), data transmission problems will occur, thus Cause system failure, so when the clock pulse is disordered, the system should be required to deal with the failure through alarm or report status. Specifically, if the clock is lost, the processor will cause an error due to a small number of pulses; if the signal duty cycle changes, within a certain enable time (such as the signal's high level or low level), processing The enable time of the device becomes shorter, which may cause misoperation. For example, the patent number is ZL02232556.5 and the application ...

AI Technical Summary

Problems solved by technology

Specifically, if the clock is lost, the processor will cause an error due to a small number of pulses; if the duty cycle of the signal changes, within a certain enable time (such as the high level or low level of the signal), the processing The device will cause misoperation due to the shortened enable time

For example, the patent number is ZL02232556.5 and the application number is 00116862.2. These two patents use the rising edge or falling edge of the measured signal to reset the counter. Therefore, when the clock is not disordered, but due to some external factors (such as the insertion of a circuit board) introduces glitches, which generally do not affect the system due to their extremely short duration, but at this time the counter will be cleared in advance, resulting in false alarms

If the above solution is built with discrete components, when the clock frequency is high, the delay between devices will cause misoperation; when built in programmable devices, due to the large number of devices, when any clock changes, the detection The ratio n of the clock and the monitored clock changes, so the clearing value of the counter changes, and the connection of the corresponding upper and lower resistors and other devices is troublesome, which is not conducive to debugging

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