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Coding device and coding method

A decoding device and decoding technology are applied in the field of decoding devices and decoding, and can solve the problems of false synchronization and synchronization of synchronization code error detection, pseudo synchronization of synchronization code and synchronization deviation, deviation and the like

Inactive Publication Date: 2005-06-01
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0017] The main purpose of the present invention is to provide an encoding device and a decoding device that can solve the problems of false synchronization and synchronization deviation caused by misdetection of synchronization codes
[0018] A more specific object of the present invention is to provide an encoding device and an encoding device capable of solving the problems of false synchronization and synchronization deviation caused by misdetection of synchronization codes when error correction / detection encoding is combined with a synchronization recovery method using synchronization codes. decoding device

Method used

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  • Coding device and coding method
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  • Coding device and coding method

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Embodiment 1

[0097] FIG. 1 is a motion diagram showing a combination of an encoding device having an error correction / detection code switching function of the present invention and a high-efficiency compression encoding device using discrete cosine transform encoding, which is one of motion compensation adaptive prediction and orthogonal transform encoding. A block diagram of Embodiment 1 of the image encoding device. Regarding the encoding method combining adaptive prediction with motion compensation and discrete cosine transform encoding, for example, there are detailed descriptions in Document 1: Edited by Hiroshi Yasuda, "International Standards for Symbolization of Malchi Media", Maruzen, (June 2013), etc. Note, therefore, only an overview of the action is described here. In addition, the error correction / detection codes used in this embodiment are codes separated into information bits and check bits like BCH codes.

[0098] In FIG. 1, an input video signal 131 to be coded which is i...

Embodiment 2

[0171] Next, Embodiment 2 of the present invention will be described with reference to FIGS. 12 to 14 . Even if the moving image encoding device and moving image decoding device of the present embodiment use a transmission path / storage medium in which a part of a bit sequence is eliminated to reduce the number of bits or add extra bits to increase the number of bits, the code sequence is transmitted / stored. , can also be reliably detected synchronously.

[0172] FIG. 12 is a block diagram showing the principle of processing for synchronous detection at the time of such bit addition / deletion. Here, as shown in FIG. 12( a ), a correct synchronization code is composed of "0" of sync_0_len bits and "1" of 1 bit. "X" in FIG. 12 is a bit other than the synchronization code.

[0173] 12(b) to (e) show how the synchronization code changes due to bit addition / deletion. Here, the number of bits (Nid) to be added / disappeared is 1 bit at most. (b) is a case where one bit is deleted in...

Embodiment 3

[0221] Next, Embodiment 3 of the present invention will be described. The difference between this embodiment and Embodiment 1 and Embodiment 2 is that no error correction / detection code is used.

[0222] Fig. 18 is a block diagram of the moving picture coding apparatus of this embodiment. Parts corresponding to those in FIG. 1 are denoted by the same reference numerals and will be described focusing on differences from Embodiment 1. In this embodiment, the structure and operation of the output encoding device 200 are different. The basic operation of the multiplexer 111 is the same as that of the multiplexer 111 in FIG. 1, but only the multiplexed code string 201 and the synchronization code insertion request signal 203 are output as the error correction / detection code is not used.

[0223]FIG. 19 is a block diagram showing the configuration of the output encoding device 200 in FIG. 18 . The output encoding device 200 is composed of a counter 1701 for counting the number of ...

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Abstract

A decoding device and decoding method for solving the problem of false synchronization or synchronization deviation caused by misdetection of synchronization codes in an encoding device using error correction / detection coding and a synchronization recovery method using synchronization codes in combination . It has an encoding unit 212 that encodes the input multiplexed code string 201 into an error correction / detection code composed of information bits and check bits, and inserts a synchronization code into the code string 201 into a plurality of predetermined periodic synchronization codes. A code string combining unit that inserts one of the positions, arranges the information bit at any position in the code string, and arranges the check bit at a position other than the insertion position of the synchronization code in the code string 201 to form the output code string 205 213.

Description

[0001] This application is a divisional application of a Chinese invention patent application with an application date of March 18, 1997, an application number of 97193909.8, and an invention title of "encoding device and decoding device". technical field [0002] The present invention relates to a system for transmitting / storing information through a medium with a high bit error rate such as a wireless transmission line, performing error correction / detection coding on a compressed code string obtained by high-efficiency compression coding, and encoding / decoding for transmission / storage code device. Background technique [0003] For example, as in wireless television (TV) telephones, portable information terminals, and digital TV broadcasting systems, it is necessary to efficiently compress and encode and transmit through wireless transmission lines to reduce image and sound information to as little information as possible. In the system, due to the high bit error rate of th...

Claims

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Application Information

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IPC IPC(8): G11B27/30H04J3/06H04L1/00H04N7/24H04N7/50H04N7/56H04N7/66H04N19/89H04N21/2383
CPCH04J3/0602H04J3/0605H04J3/07H04L1/004H04L1/0045H04L1/0075H04N7/56H04N21/234318H04N21/235H04N21/2383H04N21/2404H04N21/242H04N21/435H04N19/89H04N19/68H04N19/61G11B27/3027H04L1/0041H04L1/0083H04N21/43072H03M13/00
Inventor 菊地义浩渡边敏明驮竹健志中条健永井刚
Owner KK TOSHIBA
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