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Circuit and method for testing embedded dram circuits

A memory and tester technology, applied in the field of circuits, embedded dynamic random access memory circuits

Inactive Publication Date: 2005-10-12
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for high-volume products with many eDRAMs, the main contribution of cost-effective products comes from high-volume eDRAMs

Method used

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  • Circuit and method for testing embedded dram circuits
  • Circuit and method for testing embedded dram circuits
  • Circuit and method for testing embedded dram circuits

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Embodiment Construction

[0030] Please refer to the attached drawings and the detailed description of the preferred embodiments of the present invention. In the following description, known functions or structures are not described in detail to avoid obscuring the content of the present case.

[0031] The present invention provides a circuit and method for testing an embedded DRAM (eDRAM) circuit through a test controller with direct access mode (DA mode) logic. figure 1 is a block diagram illustrating a test system including a memory device, such as an eDRAM, including a test controller with direct access mode logic, in accordance with the present invention. see figure 1, a memory or logic tester 101 is coupled to an ASIC (Application Specific Integrated Circuit) 101 , which includes a test controller 102 and at least one embedded DRAM (eDRAM) 103 . The eDRAM 103 includes a plurality of word lines disposed at intersections of the word lines and bit lines. The test controller 102 further includes...

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Abstract

A circuit and method for testing an eDRAM through a test controller with direct access (DA) mode logic is provided. The circuit and method of the present invention allows the testing of eDRAMs with a conventional memory tester. The present invention provides a semiconductor device including an embedded dynamic random access memory (eDRAM) for storing data, the eDRAM including a plurality of memory cells; and a test controller for testing the plurality of memory cells to determine if the cells are defective, the test controller including built-in self-test (BIST) logic circuitry for performing tests and for interfacing to a logic tester; and direct access mode logic circuitry for interfacing the eDRAM with an external memory tester. The test controller further comprises a multiplexer for multiplexing data, commands, and addresses from the BIST logic circuitry and the direct access mode logic circuitry to the eDRAM.

Description

technical field [0001] The present invention relates to a semiconductor device design, and more particularly to a circuit and method for testing an embedded dynamic random access memory (eDRAM) by a test controller with direct access mode (DA mode) logic circuit. [0002] Description of related technologies Background technique [0003] In order to achieve fast production and high yield, any standard DRAM and embedded DRAM circuit needs intensive testing. Each DRAM includes redundant word lines and bit lines so that defective memory cells can be repaired. Most commonly used DRAM tests are used to find all possible memory cell errors, which are then collected in a so-called fail bit map. From this error bitmap, an external tester calculates the best use of redundancy on the chip. [0004] DRAM embedded in an ASIC (Application Specific Integrated Circuit) requires a different test strategy than standalone computer commodity DRAM. Embedded DRAM (eDRAM) typically includes a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/14G11C29/48
CPCG11C29/14G11C29/48G11C29/72G11C29/814
Inventor T·博伊赫勒
Owner INFINEON TECH AG
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