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Test of RAM address decoder for resistive open defects

A technology of electronic circuits and logical addresses, applied in the field of testing integrated circuits

Inactive Publication Date: 2011-08-17
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0040] These defect types lead to considerable consumer returns and reliability issues

Method used

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  • Test of RAM address decoder for resistive open defects
  • Test of RAM address decoder for resistive open defects
  • Test of RAM address decoder for resistive open defects

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0076] Figure 7 A jump representation indicating the need to override a resistive open defect that causes a slow rising open defect. The first and last addresses in the figure represent the first and last memory locations of a Z-block.

[0077] As mentioned, there are differences between:

[0078] - The subblock has been enabled and has access to its rows.

[0079] - both enable the subblock and have access to its rows.

[0080] According to an exemplary embodiment of the present invention, in order to detect the class of open-circuit defects causing slowly falling resistors, a sub-block of the matrix must have been enabled, and then the method includes enabling only the most recent row for previous accesses, in order to verify Steps for the "very small jump" condition. This indicates that subblocks: Z-block, U-part, cluster and sub-cluster are already enabled during the sensitization operation by accessing a row (even / odd), and only jump to the next row belonging to the ...

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Abstract

A new test pattern which consists of performing ''very small jumps'' and ''very big jumps'' within the matrix. The ''very small jumps'' are controlled by the row decoder, and have the effect of sensitizing the resistive open defects which lead to slow-to-fall behavior in the word line. A ''very small jump'' means that the memory position of two consecutive accesses remains in a unique sub-clusteruntil all rows in that sub-cluster have been tested, remains in the same cluster until all rows in that cluster have been tested, remains in the same U section until all rows in that U section have been tested, and finally, remains in the same Z block until all of the rows of that Z block have been tested. The ''very big jumps'' are intended to cover the class of resistive open defects which leads to slow-to-rise behavior, and is intended to mean that two consecutive memory accesses must never stay in the same subcluster, at the same cluster, or at the same U section.

Description

technical field [0001] The present invention relates to methods and apparatus for testing integrated circuits, such as semiconductor memory address decoders or random logic circuits, and more particularly, to methods and apparatus for testing such circuits in the presence of open defects. Background technique [0002] The systematic and automated testing of electronic circuits and especially integrated circuits is becoming increasingly important. Each generation of circuits tends to include higher component densities and more and more system functions. Individual circuits have become so complex that process defects cannot be detected and located except through exhaustive and expensive testing. It will be appreciated that consumers cannot be expected to accept that their hidden defects are revealed only during operational use, thus rendering eg life support systems or aircraft control systems unreliable. Therefore, it is of the utmost importance that manufacturers and consu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/00G11C29/02G11C29/10
CPCG11C29/10G11C29/02G01R31/28
Inventor M·阿兹曼
Owner NXP BV