Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor device and method of manufacture

A semiconductor and device technology, applied in the field of manufacturing semiconductor devices, can solve the problems of polluting manufacturing equipment, reducing output, missing the top of sidewall spacers 11, etc., achieving the effect of achieving high integration and suppressing short circuits

Inactive Publication Date: 2006-10-18
SHARP KK
View PDF2 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0015] However, in the case of the sidewall spacer 11 of a shape protruding higher than the height of the gate electrode 10 like the prior art method shown in FIG. Physical damage or the like in the cleaning step between the silicide formation steps, so that the top part of the sidewall spacer 11 is lost, indicating the possible presence of particles
As a result, there are problems of contamination of manufacturing equipment due to the occurrence of particles, and a significant decrease in yield related to the adhesion of particles to semiconductor substrates

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device and method of manufacture
  • Semiconductor device and method of manufacture
  • Semiconductor device and method of manufacture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0067] Embodiment 1 is a case where the silicidation of the surface of the gate electrode and the silicidation of the source-drain regions are performed simultaneously.

[0068] Referring to FIG. 1(A), similarly to the prior art, by providing an element isolation region 2 on the surface of a silicon substrate as a semiconductor substrate 1, a plurality of separated element regions are formed. Next, over semiconductor substrate 1 , gate insulating film 3 and polysilicon layer 4 are accumulated.

[0069] Referring to FIG. 1(B), on the polysilicon layer 4, a first insulating layer 5 is accumulated. As the first insulating layer 5, a silicon nitride film is used. The thickness of the first insulating layer 5 is desirably 1400 Ȧ. With this structure, as described below, when polysilicon layer 4 and gate insulating film 3 are etched, not all of first insulating layer 5 is etched. In addition, not all of the first insulating layer 5 is etched when the second insulating layer 7 to ...

Embodiment 2

[0083] This embodiment is a case where the silicidation of the gate electrode surface and the silicidation of the source-drain regions are performed in different steps.

[0084] refer to Figure 5 (A), similar to Embodiment 1, by providing element isolation region 2 on the surface of semiconductor substrate 1, a plurality of separated element regions are formed. Over semiconductor substrate 1 , gate insulating film 3 and polysilicon layer 4 are accumulated.

[0085] refer to Figure 5 (B), on the polysilicon layer 4 , accumulate the first insulating layer 5 . As the first insulating layer 5, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used. Also, the first insulating layer 5 may be a laminated structure so that a silicon oxide film of 5 to 50 nm is grown on the polysilicon layer 4, and a silicon nitride film or a silicon oxynitride film of 70 to 190 nm is grown thereon.

[0086] Next, refer to Figure 5 (C) and 5(D), on the first insulati...

Embodiment 3

[0101] Embodiment 3 relates to a modified example of Embodiment 2. Although the case where a two-layer structure is used for the interlayer insulating film has been described in Embodiment 2, it may be possible as Figure 9 Shown using a monolayer structure. This semiconductor device is formed such that in Figure 8 In the step of (M), the contact hole 15 and the metal wiring 14 are directly formed in the first interlayer insulating film 13 after the still unreacted high-melting-point metal film is removed.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Above semiconductor substrate 1 via gate insulation film 3, gate electrode 10 is formed having first insulation layer 5 formed on a top surface of gate electrode 10. On semiconductor substrate 1, second insulation layer 7 is formed in such a manner that the side walls of gate electrode 10 and the top surface of first insulation layer 5 are covered. Second insulation layer 7 is etched back in order to form side wall spacers 11 on the side walls of gate electrode 10 and to expose the surface of an element region. First insulation layer 5 is removed off the surface of gate electrode 10. On the surface of semiconductor substrate 1, high-melting-point metal film 8 is formed in such a manner that the top surface of gate electrode 10 and the surfaces of source-drain regions 1 b are covered, and thereafter, annealing is carried out thereby siliciding the top surface of gate electrode 10 and the surfaces of source-drain regions 1 b in order to form silicide layers 9. According to the present invention, even if the height of the gate electrode is made low, short circuiting between the gate electrode and the source-drain regions is prevented.

Description

technical field [0001] The present invention relates generally to methods of fabricating semiconductor devices, and more particularly to improved methods of fabricating semiconductor devices to enable thinning of gate electrodes, to handle refinement of the device structure, and to enable high integration of semiconductor devices. The invention also relates to semiconductor devices obtained by this method. Background technique [0002] Currently, for high-speed operation of circuit elements, this technique is used in order to reduce wiring resistance by siliciding the element region. [0003] A method of manufacturing a conventional semiconductor device will be described. [0004] Referring to FIG. 14(A), on a semiconductor substrate 1, an element isolation region 2 is formed to separate the element region from other element regions, and thereon, a gate insulating film 3 and a polysilicon layer 4 are accumulated. [0005] Referring to FIG. 14(B), a resist pattern 6 is form...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L21/823418H01L21/823443H01L21/823468H01L21/24H01L21/18
Inventor 濑良田刚榎本修治
Owner SHARP KK
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com