Clock generating circuit and glossary TV and broadcast data sample circuit
A technology for generating circuits and circuits, applied in electrical digital data processing, simultaneous/sequential multi-TV signal transmission, television, etc., and can solve problems such as incorrect sampling of data
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no. 1 example
[0047] Figure 9 A circuit block diagram schematically showing the circuit structure of the teletext broadcast data sampling circuit 900 according to the first embodiment of the present invention. exist Figure 9 In , the same circuit blocks as those in FIG. 4 are denoted by the same reference numerals as those in FIG. 4 . The teletext data sampling circuit 900 of the teletext broadcast according to this embodiment includes a slice level generating circuit 904, a comparator 401, a sampling clock generating circuit 902, and a data sampling circuit 403 for generating data.
[0048] A text signal is supplied to the slice level generating circuit 904, and the slice level generating circuit 904 outputs a slice level corresponding to the text signal. The slice level and the text signal are supplied to the comparator 401 . Then the comparator 401 compares the level of the text signal with the slice level as the reference signal, and outputs the slice data of the binary signal. The ...
no. 2 example
[0077] reference below Figure 16 18 to 18 describe the second embodiment of the teletext data sampling circuit of the present invention. Figure 16 A circuit block diagram of the teletext data sampling circuit of the second embodiment is shown. Basic structure and reference Figure 10 The first embodiment described is the same.
[0078] Apart from Figure 10 In addition to the structure, the maximum and minimum value difference detection circuit 1607, error detection circuit 1608, data holding circuit 1609 and selector are added. Circuit blocks other than those described above will not be described here since they are already covered by the first embodiment. The maximum and minimum value difference detection circuit 1607 detects the difference between the maximum value and the minimum value in the output pulse timings of the maximum value detection circuit 1001 and the minimum value detection circuit 1002 . The error detection circuit 1608 detects errors in the output co...
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