Method of manufacturing a flash memory device

Abstract

A method of manufacturing flash memory devices, wherein in a peripheral region, a polysilicon layer is formed to extend on an isolation film at the interface of an active region and the isolation film. The isolation film that has been partially wet-etched is over etched when removing a dielectric layer. It is thus possible to prevent a thinning phenomenon in which a gate oxide film is made thin. As a result, a breakdown voltage of an oxide film, which occurs in the gate oxide film, can be prevented. Furthermore, characteristics of transistors can be prevented. In addition, resistance of about several hundreds ohm / square, of the polysilicon layer can be formed.

Description

technical field [0001] The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a flash memory device capable of preventing a thinning phenomenon of a gate oxide Gate (SAFG) occurs in the peripheral region. Background technique [0002] In the manufacture of NAND flash memory devices, process tolerances decrease as device dimensions decrease. This results in reduced alignment tolerances of the polysilicon layer and the floating gate used as the active region of the cell. To solve this problem, SAFG is applied, as will be described in detail below. [0003] A sacrificial film is deposited on the semiconductor substrate defining the cell region and the peripheral region. The sacrificial film and semiconductor substrate are etched to a predetermined depth to form trenches. An oxide film is deposited such that the trenches are buried. The oxide film is polished by chemical mechanical pol...

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Problems solved by technology

In particular, it is more susceptible to damage by high-voltage NMOW (HVNMOS) transistors using voltages close to 20V or higher

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