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System and method for processing thread groups in a SIMD architecture

A thread and pipeline technology, applied in the field of single instruction multiple data processing, can solve the problem of insufficient utilization of hardware resources and achieve the effect of reducing hardware requirements

Active Publication Date: 2007-06-20
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In general, increasing the number of data paths in a SIMD processor will allow more data to be processed in parallel and will result in improved performance
However, processor size constraints limit the number of data paths to no more than a certain number
Also, if the number of data paths is too large, there may be underutilization of hardware resources

Method used

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  • System and method for processing thread groups in a SIMD architecture
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  • System and method for processing thread groups in a SIMD architecture

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Embodiment Construction

[0017] 1 is a simplified block diagram of a computer system 100 implementing a graphics processing unit (GPU) 120 with an interface unit 122 coupled to a plurality of SIMD processors 124-1, 124-2, . . . , 124-N. SIMD processor 124 accesses local graphics memory 130 through memory controller 126 . GPU 120 and local graphics memory 130 represent a graphics subsystem that is accessed by central processing unit (CPU) 110 of computer system 100 using drivers stored in system memory 112 .

[0018] The invention is applicable to any processing unit having one or more SIMD processors 124 . Thus, N can be any integer greater than or equal to one. Also, a processing unit including SIMD processor 124 may be a CPU, GPU, or any other type of processing unit.

[0019] Figure 2 illustrates in more detail a SIMD processor according to an embodiment of the present invention. As shown, the SIMD processor 200 (which may be any one of the SIMD processors 124 shown in FIG. 1 ) includes an instr...

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Abstract

A SIMD processor efficiently utilizes its hardware resources to achieve higher data processing throughput. The effective width of a SIMD processor is extended by clocking the instruction processing side of the SIMD processor at a fraction of the rate of the data processing side and by providing multiple execution pipelines, each with multiple data paths. As a result, higher data processing throughput is achieved while an instruction is fetched and issued once per clock. This configuration also allows a large group of threads to be clustered and executed together through the SIMD processor so that greater memory efficiency can be achieved for certain types of operations like texture memory accesses performed in connection with graphics processing.

Description

technical field [0001] Embodiments of the invention relate generally to single instruction multiple data (SIMD) processing, and more particularly, to a system and method for processing thread groups in a SIMD processor. Background technique [0002] A SIMD processor associates a single instruction with multiple data paths to allow the hardware to efficiently execute data-parallel algorithms. A general benefit of a SIMD processor implementation results from the reduction in pipeline control hardware and instruction processing resulting from running multiple data paths in tandem. [0003] In general, increasing the number of data paths in a SIMD processor will allow more data to be processed in parallel and will result in improved performance. However, processor size constraints limit the number of data paths to no more than a certain number. Also, if the number of data paths is too large, there may be underutilization of hardware resources. Contents of the invention [0...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F15/80
CPCG06F9/3887G06F9/3851G06F9/3885G06F9/3838G06F9/3869
Inventor 布雷特·W·库恩约翰·埃里克·林霍尔姆
Owner NVIDIA CORP
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