Apparatus and method for distribution of signals from a high level data link controller to multiple digital signal processor cores
a technology of digital signal processor and high-level data link controller, applied in the field of data processing systems, can solve the problems of increasing the magnitude and complexity of the application to which the digital signal processor is applied, increasing the need for greater computational power, and inefficient use of semiconductor materials and components
Inactive Publication Date: 2003-05-15
TEXAS INSTR INC
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Problems solved by technology
As the applications to which the digital signal processor has been applied have increased in magnitude and complexity, the need greater computational power has increased.
However, the result of provision of a complete set of interface units with each subsystem is an inefficient use of the semiconductor material and components that are not efficiently used.
Method used
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[0016] FIG. 1 has been described with respect to the related art.
[0017] Referring to FIG. 2A, a block diagram illustrating the subsystems of a data processing system 2 capable of advantageously using the present invention is shown. The data processing system 2 includes a data processing subsystem 20, a shared memory subsystem 23 and a communication subsystem 25. The data processing subsystem 20 includes a plurality of digital signal processing subsystems 21A through 21N. The communication subsystem includes a global direct memory access unit 251 and a plurality of signal exchange ports 25A through 25M. Each digital signal processor subsystem 21A through 21N is coupled to the shared memory subsystem 24 by a cache memory unit bus represented by a solid line. Each digital signal processor subsystem 21A through 21N is coupled to the communication subsystem 25 by a configuration bus represented by a dotted line and each digital signal processor subsystem 21A through 21N is ...
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In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem. In response to a predetermined condition, the signal groups are forwarded to the identified digital signal processor subsystem. The channel block unit, in response to preselected signal groups, can direct the packet to a digital signal processor subsystem that is different from the digital signal processor subsystem identified by the address signal group.
Description
[0001] U.S. patent application (Attorney Docket Number TI-32606), entitled APPARATUS AND METHOD FOR RESPONDING TO A INTERRUPTION OF A PACKET FLOW TO A HIGH LEVEL DATA LINK CONTROLLER IN A SIGNAL PROCESSING SYSTEM, invented by Ramesh A. Iyer, Henry D. Nguyen, Patrick J. Smith, and Jay B. Reimer, filed on even date herewith and assigned to the assignee of the present Application; and U.S. patent application (Attorney Docket Number TI-32605), entitled APPARATUS AND METHOD FOR CONTROLLING BLOCK SIGNAL FLOW IN A MULTI DIGITAL SIGNAL PROCESSOR CONFIGURATION FROM A SHARED PERIPHERAL DIRECT MEMORY CONTROLLER TO HIGH LEVEL DATA LINK CONTROLLER, invented by Patrick J. Smith, Jay B. Reimer, Ramesh A. Iyer and Henry D. Nguyen, filed on even date herewith and assigned to the assignee of the present Application are related Applications.[0002] 1. Field of the Invention[0003] This invention relates generally to data processing systems and, more particularly, to data processing systems having multip...
Claims
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Login to View More IPC IPC(8): G06F3/00G06F15/173G06F13/16G06F13/28G06F15/167G06F15/177H04L29/06H04L29/08
CPCG06F13/1652H04L69/324H04L29/06H04L9/40
Inventor SMITH, PATRICK J.REIMER, JAY B.IYER, RAMESH A.NGUYEN, HENRY D.
Owner TEXAS INSTR INC