Vibration-assisted method for underfilling flip-chip electronic devices

Abstract

A semiconductor assembly comprising an integrated circuit chip with a first plurality of metallic contact pads exposed, having a pitch center-to-center of less than 180 μm. A metallic bump of reflowable metal is attached to each of these contact pads. The assembly further has an electrically insulating substrate with a second plurality of metallic terminal pads in locations matching the locations of the contact pads. Each of the bumps also attached to these matching terminal pads, respectively, whereby the chip is interconnected with the substrate spaced apart by a gap. An adherent polymeric encapsulant fills the gap so that the encapsulant is free of voids. It is a pivotal feature in the method that vibration energy, up to ultrasonic frequencies, is used while the encapsulant is still in a low-viscosity precursor state in order to ensure the void-free spreading of the precursor throughout the gap between chip and substrate. The vibration energy ensures uniform underfill distribution even when the gap and the bump pitch are narrow, with uniform distribution of any fillers, and enhanced adhesion to chip, substrate and bumps.

Description

FIELD OF THE INVENTION [0001] The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to the method of void-free underfilling the gap of flip-chip electronic assemblies. DESCRIPTION OF THE RELATED ART [0002] It is known to mount an integrated circuit chip to a printed circuit substrate by solder bump interconnections. The integrated circuit chip is spaced apart from the printed circuit substrate by a gap. The solder bump interconnections extend across the gap and connect contact pads on the integrated circuit chip to terminal pads on the printed circuit substrate to attach the chip and then conduct electrical signals, power and ground potential to and from the chip for processing. There is a significant difference between the coefficient of thermal expansion (CTE) between the semiconductor material used for the chip and the material typically used for the substrate; for instance, with silicon as the semiconductor...

AI Technical Summary

Benefits of technology

[0011] It is a technical advantage of the present invention that a wide variety of solder alloys and reflow temperatures can be employed for the stress-reduced packages.

[0012] Another technical advantage is the possibility to apply the new methodology to plastic assembly boards with solder bumps for a wide variety of applications.

[0013] Other technical advantages of the present invention include an improved reliability of the assembled device.

Problems solved by technology

These stresses tend to fatigue the solder bump interconnections, resulting in cracks and thus eventual failure of the assembly.

It is well known in the industry that the elevated temperature and the temperature cycling needed for this curing can also create mechanical stresses which can be detrimental to the chip and the solder interconnections.

The stresses may delaminate the solder joint, crack the passivation of the chip, or propagate fractures into the circuit structures.

These approaches become increasingly insufficient as the number of bump interconnections increases and the bump size and the bump center-to-center pitch shrink.

With these trends, the number of voids in the underfill and the risk of clustering the fillers in the precursor increase sharply; in addition, the adhesion of the underfill to the chip, substrate, and bumps degrades.

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