Memory device having an electron trapping layer in a high-K dielectric gate stack

Abstract

An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation-in-part application from U.S. patent application Ser. No. 10 / 123,263, filed Apr. 15, 2002, entitled “Method and Apparatus for Forming a Memory Structure Having an Electron Affinity Region”, Attorney Docket No. 01-899, which is hereby incorporated by reference.TECHNICAL FIELD [0002] The invention described herein relates generally to semiconductor memory devices and to methods of their manufacture. In particular, the invention relates to memory devices having an electron trapping layer in the high-K dielectric gate stack. BACKGROUND [0003] One type of semiconductor memory device uses two different dielectric materials forming layers in the channel region of the device to form a charge storage center. The interfacial region between the two different dielectric materials forms an electron trapping region that creates the charge storage center. Such devices are often referred to as MIOS (metal insulator ox...

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Benefits of technology

[0008] In accordance with the principles of the present invention, the invention includes structures and method for forming improved semiconductor memory structures. One embodiment uses a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack i

Problems solved by technology

However, such memory structures also suffer from some drawbacks.

One drawback is that the interfacial charge storage layer 109 between the first dielectric layer 104 and the second dielectric layer 107 is difficult to form reproducibly and reliably.

Additionally, interfacial charge storage layers 109 formed in this manner suffer from unpredictable electron trapping properties, further adding to their unpredictability and reliability problems.

This inability to reliably and reproducibly fabricate interfacial charge storage layers leads to unpredictable and inconsistent behavior in

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