Process for electroplating metals into microscopic recessed features

Abstract

Several techniques are described for reducing or mitigating the formation of seams and / or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams / voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.

Description

REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority from U.S. Provisional Patent Application 60 / 105,699, filed Oct. 26, 1998, which is incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] This invention relates to electroplating and, in particular, to electrochemical deposition of metals, most particularly to the electrochemical deposition of copper into microscopic recessed features such as high aspect ratio trenches and vias as may occur in the fabrication and packaging of integrated circuits. [0004] 2. Description of Related Art [0005] The art of integrated circuits is moving irresistibly towards increased density of components and faster operating speeds. One problem encountered in decreasing.-the size of components fabricated on an integrated circuit relates to the conductivity of metallic interconnections. Conventional integrated circuits use aluminum as a conductor but for future generations of submicron component...

AI Technical Summary

Benefits of technology

The present invention addresses the challenge of preventing seams and voids in the electroplating process used to provide metal contacts and conductors in integrated circuits. The invention describes techniques for improving the quality of feature walls and bottom, including cathodic polarization and diffusion-controlled electroplating. Additionally, the invention describes a preliminary plating step and techniques for filling low aspect ratio features using conformal electroplating techniques. Overall, the invention aims to improve the efficiency and reliability of integrated circuit manufacturing processes.

Problems solved by technology

However, as integrated circuit features become ever smaller, electroplating without the formation of seams and / or voids becomes more challenging.

Deposit of a conducting seed layer onto a substrate and microscopic recessed features often does not provide adequate metallization of the feature walls, leading to poor electroplating.

The poor electrical quality of feature sidewalls and bottom is observed to worsen when the substrate is brought into contact with the electroplating solution.

Images