Polishing slurry, method of producing same, and method of polishing substrate

Abstract

Disclosed is a polishing slurry, particularly, a slurry for chemical mechanical polishing, which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention provides a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 μm or less) and which decreases the occurrence of scratches on a flattened surface, and a method of polishing a substrate using the same.

Description

BACKGROUND OF THE INVENTION [0001] This application claims the priority of Korean Patent Application No. 2004-0059245, filed on Jul. 28, 2004, 2004-0059246, filed on Jul. 28, 2004, 2004-0067536, filed on Aug. 26, 2004 and 2004-0118158, filed on Dec. 31, 2004 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. [0002] 1. Field of the Invention [0003] The present invention relates to a polishing slurry, particularly, a slurry for chemical mechanical polishing (hereinafter, referred to as ‘CMP’), which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention pertains to a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 μm or less) and which d...

AI Technical Summary

Benefits of technology

[0012] Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a high performance nano ceria slurry which is capable of being applied in a process of producing ultra highly integrated semiconductors of 0.13 μm or less, particularly, an STI process, and is capable of minimizing micro-scratches that are fatal to semiconductor devices by properly employing a method and a device for pre-treating various particles, a dispersing device and a method of operating the dispersing device, a method of adding a chemical additive and an amount added, and a device for transferring samples.

[0015] Based on the above description, the present invention aims to provide a slurry that is capable of minimizing micro-scratches and maintaining a suitable removal rate and in which dispersion is stabilized.

[0016] Another object of the present invention is to provide a method of effectively polishing a semiconductor substrate having a fine design rule using the above slurry.

[0017] In order to accomplish the above objects, the present invention provides a polishing slurry which comprises polishing particles in which a surface area per unit weight is changed so as to minimize agglomeration of the polishing particles and improve dispersion stability.

Problems solved by technology

However, the use of the additive is disadvantageous in that the removal speed of the oxide layer, as well as the removal speed of the nitride layer, is reduced.

Furthermore, the polishing agent of the ceria slurry typically has particles larger than those of the silica slurry, and therefore scratches the surface of the wafer.

However, if polishing speed selectivity of the oxide layer to the nitride layer is low, a dishing phenomenon, in which an excessive volume of the oxide layer is removed, occurs due to the loss of adjacent nitride layer patterns.

Thus, it is impossible to achieve uniform surface flattening.

However, the above prior arts disclose only the average particle size of the polishing particles constituting the polishing slurry and the range thereof, but lack details on how to disperse the particles.

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