Method, system, and program product for accommodating spatially-correlated variation in a process parameter

Abstract

The invention provides a method, system, and program product for accommodating spatially-correlated variation in a process parameter during statistical timing of a circuit. In one embodiment, the method includes dividing an area of the circuit into a plurality of grid cells; associating an independent random variable with each of the plurality of grid cells; and expressing at least one spatially-correlated parameter of a first grid cell as a function of the random variables associated with the first grid cell and at least one neighboring grid cell.

Description

BACKGROUND OF THE INVENTION [0001] 1. Technical Field [0002] The invention relates generally to statistical timing of a circuit, and more particularly, to a method, system, and program product for accommodating spatially-correlated variation in one or more process parameters during statistical timing of a circuit. [0003] 2. Background Art [0004] As the sizes of transistors and interconnects in integrated circuits have decreased, variabilities in process parameters have led to corresponding increases in the difficulty of modeling and predicting circuit performance. Variations in process parameters can be inter-die variations (i.e., variations from die to die) or intra-die variations (i.e., variations within a single chip). Inter-die variations affect all components on a single chip similarly, while intra-die variations affect similar components on a single chip differently. [0005] Statistical static timing analysis (SSTA) has become a widely-recognized technique for predicting statis...

AI Technical Summary

Benefits of technology

This approach effectively models spatially-correlated variations with reduced computational expense, improving the efficiency of statistical timing analysis by using hexagonal grids to capture isotropic spatial relationships and approximating correlation functions, thus enhancing the accuracy and speed of parameterized block-based SSTA.

Problems solved by technology

As the sizes of transistors and interconnects in integrated circuits have decreased, variabilities in process parameters have led to corresponding increases in the difficulty of modeling and predicting circuit performance.

However, the approaches to parameterized block-based SSTA to date are not problem-free.

621-625, is also unsatisfactory.

However, such an approach presents computational difficulties.

Such decomposition is computationally expensive.

Due to the number of uncorrelated variables, PCA cannot reduce the number of independent variables to fewer than 2500.

Thus, using the PCA approach of Chang et al., large chips having relatively small correlation distances require a very large matrix and the computation of a prohibitively large number of eigenvalues and eigenvectors.

Other known approaches, whereby correlation coefficients are computed directly from a correlation matrix, are similarly unsatisfactory.

First, such approaches require multiplication of the correlation matrix and canonical forms.

This is both computationally expensive and adversely affects the efficiency of parameterized block-based SSTA.

Second, the use of linear forms of delays, arrival times, and required times with correlated terms complicates other necessary operations, such as the computation of standard deviations, controlling and pruning small terms, reporting results, etc.

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