Method and system for providing indeterminate read data latency in a memory system

Abstract

A method and system for providing indeterminate read data latency in a memory system. The method includes determining if a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received. The upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 11 / 289,193 filed Nov. 28, 2005, the contents of which are incorporated by reference herein in their entirety.BACKGROUND OF THE INVENTION [0002] This invention relates to memory systems comprised of hub devices connected to a memory controller by a daisy chained channel. The hub devices are attached to, or reside upon, memory modules that contain memory devices. More particularly, this invention relates to the flow control of read data and the identification of read data returned to the controller by each hub device. [0003] Many high performance computing main memory systems use multiple fully buffered memory modules connected to a memory controller by one or more channels. The memory modules contain a hub device and multiple memory devices. The hub device fully buffers command, address and data signals between the memory controller and the memory devices. The flow of...

AI Technical Summary

Benefits of technology

The patent describes a method and device for improving the speed of data transmission in a memory system. The method involves storing received data packets into a buffer device and transmitting them to an upstream driver for transmission to a memory controller. The device includes a mechanism for determining if a data packet has been received and if the upstream driver is idle, and then transmitting or storing the data packet accordingly. This method helps to minimize read data latency and enable indeterminate read data return times to the memory controller. The patent also describes a memory system with one or more memory modules and hub devices for buffering and transmitting data to the memory controller. The system uses a frame format with an identification tag and frame start indicator for efficient data transmission.

Problems solved by technology

During run time operations, these two restrictions result in additional gaps being added to packets of read data that are returned from the memory modules.

This adds latency to the average read operation.

In addition, hubs are not able to use indeterminate techniques to return read data faster or slower than normal.

Preventing data corruption by avoiding data collisions is especially complicated as hub devices merge local read data onto a cascaded memory controller channel.

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