Transistors, semiconductor integrated circuit interconnections and methods of forming the same

Abstract

Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

Description

PRIORITY STATEMENT[0001]This application claims priority under 35 USC § 119 to Korean Patent Application No. 2006-87969, filed Sep. 12, 2006, in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference.BACKGROUND[0002]1. Field[0003]Example embodiments relate to semiconductor discrete devices, semiconductor integrated circuit interconnections and methods of forming the same. Other example embodiments relate to transistors, semiconductor integrated circuit interconnections and methods of forming the same.[0004]2. Description of Related Art[0005]Transistors or semiconductor integrated circuit interconnections have been recently formed by burying a conductive layer in a trench defined by a material layer according to a gradual reduction of a design rule. The conductive layer may be formed into a buried gate of a transistor or a buried interconnection of a semiconductor integrated circuit interconnection. The material layer may be ...

AI Technical Summary

Benefits of technology

[0009]Example embodiments provide transistors and semiconductor integrated circuit interconnections suitable for improving electrical characteristics and simplifying a semiconductor fabrication process. Exampl

Problems solved by technology

However, the buried gate or the buried interconnection makes it difficult to perform a semiconductor fabrication process related to the transistor or the semiconductor integrated circuit interconnection.

The electrical nodes may contact the buried gate due to gradually reducing the design rule.

However, the buried gate may easily contact the electrical nodes of the active regions due to gradually reducing the design rule.

Images