Seal ring structure for integrated circuits

Abstract

A seal ring structure for an integrated circuit includes a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and / or RF circuit block from a noise. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. provisional application No. 61 / 057,185, filed May 29, 2008.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention related to semiconductor devices and, more particularly, to a seal ring structure for an integrated circuit that is capable of reducing substrate noise coupling.[0004]2. Description of the Prior Art[0005]Advances in fabrication technology have enabled entire functional blocks, which previously had been implemented as plural chips on a circuit board, to be integrated onto a single IC. One particularly significant development is mixed-signal circuits, which combine analog circuitry and digital logic circuitry onto a single IC.[0006]However, a major technical hurdle to implementing mixed-signal circuits has been the coupling of noise between different portions of the IC, for example, from the digital to the analog portions. Ordinarily, an integrated circui...

AI Technical Summary

Benefits of technology

The present invention provides an improved seal ring structure for an integrated circuit chip that reduces digital noise coupling from a digital circuit. This is achieved by a seal ring structure that includes a seal ring divided into two parts, a P+ region in a P substrate, and a shallow trench isolation structure surrounding the P+ region. The seal ring structure shields an analog and / or RF circuit block from noise, while the P+ region enhances the performance of the integrated circuit. The technical effects of this invention include reducing digital noise coupling, improving the performance of the integrated circuit, and shielding sensitive components from noise.

Problems solved by technology

However, a major technical hurdle to implementing mixed-signal circuits has been the coupling of noise between different portions of the IC, for example, from the digital to the analog portions.

It has been found that the noise, such as digital noise, which, for example, may be originated from a digital power signal line such as VDD or signal pad of a digital circuit, propagates through the seal ring and adversely affects the performance of the sensitive analog and / or RF circuit.

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