Col (chip-on-lead) multi-chip package

a chip-on-lead and multi-chip technology, applied in the field of chip-on-lead (col) multi-chip packages, can solve the problems of broken wires, inability to balance the upper and lower mold flows, and limited number of chips that can be stacked inside a package, so as to reduce the shifting of leads
US20090302441A1Inactive Publication Date: 2009-12-10POWERTECH TECHNOLOGY INC
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
POWERTECH TECHNOLOGY INC
Publication Date
2009-12-10
Estimated Expiration
Not applicable · inactive patent

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Abstract

A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, tile thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting.
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Description

FIELD OF THE INVENTION

[0001] The present invention relates to packaged semiconductor devices, especially to Chip-On-Lead (COL) multi-chip packages.BACKGROUND OF THE INVENTION

[0002] In the conventional semiconductor packages, leadframes have been widely implemented as chip carriers and as electrical connection media. There are several basic packaging configurations according to the features of the chip carriers such as Chip-On-Lead packages (COL), Lead-On-Chip (LOC) packages, and conventional “chip on die pad” packages where COL packages are to attach the back surfaces of the chips, i.e., the surfaces of the chips without ICs, to certain internal sections of the leads, then the chips and the leads of leadframes are encapsulated by molding. In order to balance the upper and lower mold flows during transfer molding, at least two downset bends are formed on the leads or on the tie bars of the die pad leading to shaking of the leads. Once experienced the pressure of the mold flows during m...

Claims

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