Computation of jacobian logarithm operation

Abstract

An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of first signals carrying (i) a maximum value among a plurality of input values and (ii) a plurality of difference values based on the input values. The second circuit may be configured to generate a plurality of second signals carrying a plurality of intermediate values based on the difference values. The intermediate values are generally respective powers of two. The third circuit may be configured to generate a third signal carrying an output value by adding the maximum value and the intermediate values. The output value may be a Jacobian logarithm computation of the input values.

Description

[0001]This application claims the benefit of Russian Application No. 2010152794, filed Dec. 24, 2010 and is hereby incorporated by reference in its entirety.FIELD OF THE INVENTION[0002]The present invention relates to wireless communications generally and, more particularly, to a method and / or apparatus for implementing computation of a Jacobian logarithm operation.BACKGROUND OF THE INVENTION[0003]Conventional schemes that compute a Jacobian logarithm operation commonly have a big depth. The depth limits clock frequencies on which the conventional schemes can run, which in turn restrict an overall speed of a decoder in which the max* operation is implemented. The Jacobian logarithm operation is commonly referred to as a max* operation. The max* operation is computed according to formula 1 as follows:max*(a,b)=ln(ea+eb)  (1)where a and b are real numbers. The max* operation was originally defined by Andrew J. Viterbi in 1998.[0004]The max* operation may be rewritten per formula 2 as ...

AI Technical Summary

Benefits of technology

[0009]The objects, features and advantages of the present invention include providing a method and / or apparatus for implementing computation of the Jacobian logarithm operation that may (i) give decoding quality comparable with the quality of a pure Log-MAX technique, (ii) implement the max* operation with a low depth compared with conventional techniques, (iii) compute the max* operation in less than two clock cycles, (iv) implement fully combinational logic for high speed operation, (v) incorporate ring oscillators and / or pseudo-random binary string generators to increase decoding quality where fixed point numbers are used and / or (vi) calculate a maximum value and multiple additive terms in a single circuit.

Problems solved by technology

The depth limits clock frequencies on which the conventional schemes can run, which in turn restrict an overall speed of a decoder in which the max* operation is implemented.

A disadvantage of the MAX-Log-MAP technique is a degradation in decoding quality compared with pure a Log-MAP technique.

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