Unlock instant, AI-driven research and patent intelligence for your innovation.

SOI CMOS structure having programmable floating backplate

a technology of programmable backplates and semiconductor devices, which is applied in the direction of semiconductor devices, process and machine control, instruments, etc., can solve the problem of cumbersome electrically adjacent backplates, and achieve the effect of more versatile functions

Inactive Publication Date: 2013-01-17
GLOBALFOUNDRIES INC
View PDF1 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008]Compared with the regular hard-wired (non-floating) backplate schemes, programmable floating backplates provide more versatile functions. For example, with hard-wired backplates, it is cumbersome to have adjacent backplates electrically biased at different voltages. With electrically floating backplates, each backplate can be programmed to its desired voltage without electrical circuits dedicated to maintaining the electrical bias of adjacent backplates at different voltage potentials.

Problems solved by technology

For example, with hard-wired backplates, it is cumbersome to have adjacent backplates electrically biased at different voltages.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • SOI CMOS structure having programmable floating backplate
  • SOI CMOS structure having programmable floating backplate
  • SOI CMOS structure having programmable floating backplate

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0024]Referring to FIG. 1, a first exemplary semiconductor structure according to the present invention includes a substrate 8. The substrate 8 includes, from bottom to top, a handle substrate 10, a first buried insulator layer 20, an unpatterned buried conductive material layer 34L, an unpatterned second buried insulator layer 40L, and an unpatterned top semiconductor layer 41L. The unpatterned buried conductive material layer 34L constitutes the entirety of a buried conductive layer 30, which refers to the entirety of the material above the top surface of the first buried insulator layer 20 and below the bottom surface of the unpatterned second buried insulator layer 40L at this step. The unpatterned top semiconductor layer 41L constitutes the entirety of a top semiconductor layer 50, which refers to the entirety of the material above the top surface of the unpatterned second buried insulator layer 40L at this step.

[0025]The handle substrate 10 can include a semiconductor material...

third embodiment

[0065]Referring to FIG. 6, a third exemplary semiconductor structure according to the present invention is derived from the first and second exemplary semiconductor structures by forming an n-doped semiconductor region 60 of the first exemplary semiconductor structure and an injector FET 69 of the second exemplary semiconductor structure in or on the first semiconductor layer 50.

[0066]In the third embodiment, the injector FET 69 is employed to program the buried floating conductive material portion 34 by utilizing hot electrons generated from the injector 69 and to subsequently erase the programming of the buried floating conductive material portion 34 by extracting electrons from the buried floating conductive material portion 34 to the n-doped semiconductor region 60.

[0067]The switchable power supply system is modified to enable generation of hot electrons in the injection FET 69 and extraction of electrons at the n-doped semiconductor region 60. For example, the switchable power ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application is a continuation of U.S. patent application Ser. No. 12 / 619,285, filed Nov. 16, 2009 the entire content and disclosure of which is incorporated herein by reference.BACKGROUND[0002]The present invention relates to semiconductor structures, and particularly to semiconductor structures including semiconductor devices having a programmable floating backplate, methods of manufacturing the same, and methods of operating the same.[0003]In semiconductor-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) circuits, a conductive region can be provided underneath a buried oxide (BOX) layer. Such a conductive region is typically referred to as a backplate. A conductive electrical contact is provided to the backplate, typically by a contact via that extends from a top surface of an SOI substrate to the backplate. An appropriate voltage potential can be applied to the backplate through the contact via to alter the charact...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): G05F3/02
CPCH01L27/1203H01L21/84H01L29/7841
Inventor CAI, JINDENNARD, ROBERT H.KHAKIFIROOZ, ALINING, TAK H.YAU, JENG-BANG
Owner GLOBALFOUNDRIES INC