Engineering change order hold time fixing method

Abstract

An ECO hold time fixing method fulfills a short path padding in a placed and routed design by a minimum capacitance insertion. In the method, a padding value determination step receives the placed and routed design and is based on a cell library, timing constraints, and a timing analysis report to determine padding values and locations required for each gate of the placed and routed design to output. A load / buffer allocation step is based on a spare cell information, a dummy metal information, and the padding values and locations to achieve the short path padding in the placed and routed design.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to the technical field of integrated circuits and, more particularly, to an engineering change order (ECO) hold time fixing method.[0003]2. Description of Related Art[0004]Due to a wide range of dynamic variations, e.g., supply voltage droops, process variations, temperature fluctuations, soft errors, and transistor aging degradation, the timing characterization is extremely difficult in modern IC designs. Therefore, in conventional design, designers conservatively reserve a timing guardband to ensure correct functionality even under the worst-case circumstance. However, this reserved guardband may severely degrade circuit performance, i.e., limit the clock frequency.[0005]Accordingly, several resilient circuits have been proposed to eliminate the guardband by error detection and correction. For example, a Razor flip-flop (FF) is used as an error detection circuit (See D. Ernst et al., “Raz...

AI Technical Summary

Benefits of technology

The present invention provides a method for fixing the hold time of an engineering change order (ECO) in a placed and routed design. The method uses global view to determine the padding values and locations and employs spare cells in a coarse-grained delay padding and a dummy metal in a fine-grained delay padding. This results in successful hold time fixing.

Problems solved by technology

Due to a wide range of dynamic variations, e.g., supply voltage droops, process variations, temperature fluctuations, soft errors, and transistor aging degradation, the timing characterization is extremely difficult in modern IC designs.

However, this reserved guardband may severely degrade circuit performance, i.e., limit the clock frequency.

However, these resilient circuits require a significant hold time margin for short paths.

Taking the circuit of FIG. 1 as an example, the resilient circuit may detect a false timing error if the result of the next computation is propagated through a short path and sampled by the delayed clock.

Due to the extra hold time margin requirement, the short path padding or hold timing fixing in the resilient circuits becomes more challenging.

However, such linear programming is time-consuming and not applicable to large-scale circuits.

Because of the significant hold time margin, the hold violations may still exist in a placed and routed design.

Moreover, even an optimal padding solution is found, it may still fail at a physical implementation because the delay offered by buffers is fixed.

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